Browse Prior Art Database

Built-in Self Test using a Local Microprocessor

IP.com Disclosure Number: IPCOM000106755D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Cook, DC: AUTHOR

Abstract

Disclosed is a Built-In Self Test (BIST) function which uses a local microprocessor and its associated bus in an application broken into three sections--a test sequencer, a Pseudo-Random Pattern Generator (PRPG), and a Multiple Input Signature Register (MISR).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Built-in Self Test using a Local Microprocessor

      Disclosed is a Built-In Self Test (BIST) function which uses a
local microprocessor and its associated bus in an application broken
into three sections--a test sequencer, a Pseudo-Random Pattern
Generator (PRPG), and a Multiple Input Signature Register (MISR).

      Referring to the Figure, a circuit to be tested is partitioned
into a number of testable logic blocks 5, each of which is provided
with a number of parallel inputs from a Shift Register Latch (SRL)
string 6, and each of which is provided with an equal number of
parallel outputs to another SRL string 6.  Each SRL string 6 is
comprised of a number of serially connected latches forming a shift
register.  The first SLR string 6 is provided with a number of
parallel inputs 7 from pins of the circuit module under test.  The
flow of data through the SRL strings 6, and through the associated
logic blocks 5, is controlled by pulses from Level Sensitive Scanning
Design (LSSD) A, B, and C clocks (not shown) used in the test
process.  A and B clock pulses move data serially through an SRL
string 6, from top to bottom as shown in the Figure.  C clock pulses
move data in a parallel fashion, from left to right as shown is the
figure, between SRL strings 6 and adjacent logic blocks 5.

      Test sequencer 10 controls PRPG 12 and MISR 13, and includes a
state machine which controls the LSSD A and C clocks (not shown).
The B clocks (not shown) are free running.  PRPG 12 includes a linear
feedback shift register having a length of twenty-three elements with
codes being generated in accordance with a primitive polynomial 14.
MISR 13 includes a linear feedback shift register having a length of
sixteen elements with codes generated in accordance with a primitive
polynomial 15.  The microprocessor (not shown) can access the
signature in this register by reading addresses "52" and "54."

      In self-test operation, the microprocessor performs its own
self test first.  A BIST mode is activated by writing "XXX00001" to
Register No.  1 ("50," not shown).  At this point, inputs and outputs
are tri-stated, PRPG 12 is set, and MISR 13 is reset.  Self test is
then started by writing "X1100011" to Registe...