Browse Prior Art Database

Method for Rapid Performance Analysis and Design of Semiconductor Manufacturing Facilities

IP.com Disclosure Number: IPCOM000106775D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 108K

Publishing Venue

IBM

Related People

Connors, D: AUTHOR [+3]

Abstract

Disclosed is a method for rapidly obtaining performance estimates of semiconductor manufacturing facilities. The method is based on an open queueing network model of the facility. The method uses as input a specification of relevant data about the semiconductor facility similar to what a simulation would require for input - for example, product routing information, tool reliability information, the number of tools of each type in the facility, etc. The method generates accurate estimates of all steady state performance measures of interest in usually under five minutes of computation time.

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Method for Rapid Performance Analysis and Design of Semiconductor Manufacturing Facilities

      Disclosed is a method for rapidly obtaining performance
estimates of semiconductor manufacturing facilities.  The method is
based on an open queueing network model of the facility.  The method
uses as input a specification of relevant data about the
semiconductor facility similar to what a simulation would require for
input - for example, product routing information, tool reliability
information, the number of tools of each type in the facility, etc.
The method generates accurate estimates of all steady state
performance measures of interest in usually under five minutes of
computation time.

      Also disclosed is a method for doing tool planning for
semiconductor lines.  The method is based on a marginal allocation
procedure which uses performance estimates from the queueing model to
determine the order in which to add tools to the line.  For example,
the method can be used  to determine the number of tools needed in
each tool group to achieve a target cycle time at minimal cost.
While the marginal allocation procedure could in theory be carried
out in conjunction with a computer simulation of the semiconductor
line, in practice the amount of computation time needed would be
prohibitive.  The use of the queueing model enables the marginal
allocation procedure to run quickly.

      To understand the value of the disclosed methods, it is
important to understand certain relevant aspects of semiconductor
manufacturing.  The manufacture of semiconductor devices is a highly
complex, expensive and time consuming process.  A high volume
semiconductor line consists of several hundred tools grouped into
dozens of distinct tool groups.  Collections of wafers, known as
jobs, move from tool group to tool group undergoing hundreds of
operations before completion.  Each job follows a process sequence
that corresponds to the product family to which the job belongs.  The
process sequence is specified by a consecutive list of operations to
be performed on the wafers in the job.  Typically many hundreds of
jobs belonging to different product families are circulating within
the line at any given time.

      The flow of jobs through the line is highly reentrant, meaning
that jobs make multiple visits to tool groups as successive circuit
layers are added.  Additional complexity arises from the fact that
jobs, or portions of jobs, may be scrapped or sent for rework during
the course of being processed.  Thus, the number of wafers in a job
may change as the job moves through the line.  Also, tool breakdowns,
preventative maintenance, operator unavailability, setup times and
other factors  combine to make the manufacturing environment highly
stochastic.

      Because of the enormous investment in time and money required
to build and operate a semiconductor line, it is important know what
the operating...