Browse Prior Art Database

Pipelining and Data Flow

IP.com Disclosure Number: IPCOM000106781D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 97K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+3]

Abstract

The layout of a processor becomes more easily discernible when that processor is implemented as a single chip. The data flow that must be sustained relates to the variety of inputs and output of each instruction. The attempt to complete a single instruction execution on each cycle further complicates the data flow for certain architectures more than others. These relationships are explored in this disclosure.

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Pipelining and Data Flow

      The layout of a processor becomes more easily discernible when
that processor is implemented as a single chip.  The data flow that
must be sustained relates to the variety of inputs and output of each
instruction.  The attempt to complete a single instruction execution
on each cycle further complicates the data flow for certain
architectures more than others.  These relationships are explored in
this disclosure.

      One term that is often used is describing processor
organizations is pipelining.  By instruction pipelining within an
organization one means that a subsequent instruction is started
before all prior instruction are finished.  Pipelining can be a
misused term in the context of the actual design of a processor.  It
is always the case that each instruction must see the results of the
execution of all prior instructions but when instructions are
uniformly pipelined the information need not be ready until the
station of service that requires it engages the instruction.  A
non-familiar example that illustrates this point is an instruction
with an immediate operand.  This operand needs to be used in
conjunction with an operand derived from memory.  In a pipelined
processor some agency within the data flow must maintain the
immediate operand until the arrival of the data from memory.

      Orthogonal to the question of pipelined and unpipelined
processor organization is the performance objective of the processor
organization.  If it is desired that the processor organization
achieve an instruction execution rate that approximates one cycle per
instruction then this places additional qualifications on the
processor organization.

Unpipelined 1-Cycle Processors - In unpipelined 1-cycle processor
organizations, all the information needed to execute the instruction
is current and can be referenced from register file or from the
instruction.  This implies that instructions that contain immediate
operand only interact with registers.  This also means that the
contents of registers at the decode cycle of an instruction are the
valid inputs to the instruction.  A LOAD instruction is not a
violation of these rules as it merely marks a register as unavailable
until the register is loaded from the memory.

Pipelined 1-Cycle Processors - A RISC machine and a S/370 machine
that is pipelined to achieve equivalent performance are substantially
different in this regard and the impact on the data flow needed to
sustain the instruction execution is significant.

      The pipelined 1-cycle processors, as represented by the S/370
architecture, are 1-cycle in the Execution Unit and have a sequence
of instruction pres...