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Speculative Execution using the Collision Vector Table Valid Field and the Collision Vector Table Status Register

IP.com Disclosure Number: IPCOM000106782D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Karim, F: AUTHOR [+4]

Abstract

The Collision Vector Table (CVT) is utilized in speculative execution of instructions. On conditional branches, the flow of the instructions depends on the resolution of the condition on which the branch will be taken. Where the instructions are fetched from, depends on whether the branch was taken or not. The execution of instructions that might be in the not taken path is referred to as speculative execution. This disclosure discusses the speculative execution of instructions on multi-execution unit supescalar type processors.

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Speculative Execution using the Collision Vector Table Valid Field and the Collision Vector Table Status Register

      The Collision Vector Table (CVT) is utilized in speculative
execution of instructions.  On conditional branches, the flow of the
instructions depends on the resolution of the condition on which the
branch will be taken.  Where the instructions are fetched from,
depends on whether the branch was taken or not.  The execution of
instructions that might be in the not taken path is referred to as
speculative execution.  This disclosure discusses the speculative
execution of instructions on multi-execution unit supescalar type
processors.

      Branch conditional instruction is an important facility that is
used to control the flow of instructions through the processor.
Branch conditional instructions will cause a branch to a certain
location in the instruction stream upon the fulfilment of a certain
condition in the machine.  Usually the compare instruction causes the
condition register to be set depending on the outcome of the
comparison.  For example it might be desired to branch to a certain
location,  if operand a is greater than operand b.  A comparison of a
and b will set the corresponding condition register field
appropriately,  and will cause a branch if the condition a>b is met.

Usually to improve the performance of the processor, it is more
desirable to continue fetching and executing instructions and not
wait for the condition to be resolved.  This is referred to as
speculative execution of instructions.  There has to be a way of
restoring the machine state to what it would have been if the branch
condition resolution is different from what was speculated.  This is
even more difficult in multi-execution environment.  This disclosure
describes an innovative approach to solve this problem.

      The components of the speculative execution are:  CVT, the cvt
STATUS register and the superscalar control unit (SSC).  The CVT
STATUS register has 6, 2 bit entries,  and gets set by the SSC.  Each
entry of this register represents the status of the corresponding CVT
sub-table (Fig. 1).

      The status register together with the valid bits of the CVTs
determine the system behavior in speculative execution of
instructions.  The truth tables for the CVT valid bits and the status
register fields are shown below:

      To illustrate how the speculative execution works,  an
instruction stream including a branch conditional instruction is used
as an example.  The contents of the CVT and the status register are
shown pictorially for clarity and ease of understanding.  Fig. 2
shows the instruction stream and the CVT and status register contents
corresponding to this instruction stream.

      In this Figure,  Inst.,  CMP,  BC,  Seq.,  Tar.,  stand for
instruction, compare, branch conditional, sequential, and target
respectively.  Sequential instructions are located right after the...