Browse Prior Art Database

Enhanced Charge Storage in DRAM Trench Capacitors

IP.com Disclosure Number: IPCOM000106783D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Kleinhenz, RL: AUTHOR [+2]

Abstract

Disclosed is a method for increasing the storage capacitance of trench-based DRAM cells by anisotropic etching of trench sidewalls. Neither a new mask nor any further process modifications are required.

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Enhanced Charge Storage in DRAM Trench Capacitors

      Disclosed is a method for increasing the storage capacitance of
trench-based DRAM cells by anisotropic etching of trench sidewalls.
Neither a new mask nor any further process modifications are
required.

      Dynamic RAM cells employ trench or stacked capacitors for
charge storage.  A schematic view of the basic trench-based
single-transistor cell is shown in Fig. 1a.  The trenches are
typically &app. 10 &mu.m deep and are formed by reactive ion etching
(RIE).  Reactive ion etching is a single wafer process and thus time
consuming, especially for the deeper trenches necessitated by smaller
trench cross-sectional areas of future technologies (256 Mb).

      The needed capacitance per DRAM cell is dictated by the design
rules.  The capacitance increases linearly with the area of the
trench sidewall, and thus with the trench depth.  To reduce
processing time during RIE one would like to increase the area of the
sidewall and reduce the depth to which the trench has to be etched.
Since the cross section of the trench is a basic layout feature of a
given design, it cannot be modified.  Roughening the sidewalls of the
trench by an anisotropic etch such as KOH as shown in Fig. 1b is
proposed.  Under ideal conditions this etch would create a saw-tooth
pattern at the sidewalls.

      There have been reports recently of using textured polysilicon
to increase the effective area of stacked capacitors in DRAM
applications [1,2,3,4].  These techniques have been applied
successfully to stacked capacitor based DRAM cells [1,3].  The
advantage of our scheme is that it works for trench capacitors, and
directly on single crystal silicon.  Also, the process complexity is
far less than with the previously reported schemes:  just one extra
(batch) process step (2 if followed by an isotropic etch, which may
or may not be necessary), and no extra hot process steps.  No extra
masks steps are needed.  Thus, th...