Browse Prior Art Database

Run Time Binding of First-in, First-out Port Selection

IP.com Disclosure Number: IPCOM000106794D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+3]

Abstract

An architecture for a superscalar microprocessor was devised which allows the microprocessor to have up to 8 input First In, First-out (FIFO) ports and 8 output FIFO ports. The microprocessor can attach to and receive data from 8 separate input devices, and attach to and transmit data to 8 separate output devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Run Time Binding of First-in, First-out Port Selection

      An architecture for a superscalar microprocessor was devised
which allows the microprocessor to have up to 8 input First In,
First-out (FIFO) ports and 8 output FIFO ports.  The microprocessor
can attach to and receive data from 8 separate input devices, and
attach to and transmit data to 8 separate output devices.

      This disclosed mechanism enables the FIFO sources and
destinations to be treated as objects to the program in an object
oriented sense (Figure).  The FIFO's are indirectly addressed via the
contents of the FIFO Control register.  In other words, software can
select the FIFO ports (both input and output) by setting the
appropriate bits in the FIFO Control register.  Thus, the FIFO
channel selection is bound at run time rather than at compile time.
Common routines can be written for multiple channels in which the
selection of the FIFO channel for output can be deferred until the
routine executes.  In the same way the source FIFO channel for an
operation can be selected at run time.  Consider for example a
sequence of FIFO output instructions:

        mtspr FIFOCTL,Rx   # Configure FIFO Control Register

        fogs R0            # Transmit 1st word from

                             R0 thru FIFO output port

        fogs R1            # Transmit 2nd word from

                             R1 thru FIFO output port

        fogs R2            # Transmit 3rd word from

                             R2 thru FIFO output port

        fogs R3            # Transmit 4th word from

                             R3 thru FIFO output port.

      By selecting the desired FIFO channel(s) on which to output and
transferring this information to the FIFO Control register via the
mtspr FIFOCTL, Rx instruction, the following scenarios are possible
for all subsequent FIFO output operations:

o   Output every word to any single FIFO channel.

o   Output every word to any combination of FIFO channels.

o   Do no output to...