Browse Prior Art Database

Generating Discrete I-Line Access Sequences without Monitoring I-Misses

IP.com Disclosure Number: IPCOM000106797D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 106K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

The ability to generate Discrete I-LINE Access Sequences (DIAS) for a processor is not limited to monitoring I-LINE misses. The monitoring of misses is subject to certain technical problem associated with lines already in the cache both through happenstance or as having previously missed. The DIAS sequence can be determined at any time and starting at any place using a processor-indexed MBHT and utilizing BWG indications. Such an approach is disclosed.

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Generating Discrete I-Line Access Sequences without Monitoring I-Misses

      The ability to generate Discrete I-LINE Access Sequences (DIAS)
for a processor is not limited to monitoring I-LINE misses.  The
monitoring of misses is subject to certain technical problem
associated with lines already in the cache both through happenstance
or as having previously missed.  The DIAS sequence can be determined
at any time and starting at any place using a processor-indexed MBHT
and utilizing BWG indications.  Such an approach is disclosed.

      There are several aspects involved in creating a means within
the L2 of of a multiprocessing system to perform a function that is
within the province of the processors.  These aspects involve:

o   How does information get to the L2?

o   How is the information organized?

o   How is the information updated?

o   What additional information must the L2 maintain to complete this
    additional information?

The anticipation of I-LINE MISSES from a given processor is a case in
point.  Typically the only information presented to the L2 are the
I-MISSES and this information represents the misses that occur within
a framework where omissions result from the presence of I-LINES due
to happenstance.  In seeking to dampen this cache dynamic one can
start recording misses following a purge of the I-CACHE but the
resulting miss sequence does not give the information desired as the
sequence is entered in the middle.  An earlier line that is brought
into the cache since the purge can be used subsequent to an entry and
not show up as a miss.  The organization of such a miss sequence,
once derived, does not conform to the organization of a L2-DIRECTORY
as the information about the next-miss-generated by a given I-LINE
has no basis through which it can be updated by the subsequent
occurrence of a branch wrong guess (BWG) within that I-LINE.  The
sequence required by a L2-DIRECTORY is a DIAS sequence (Discrete
I-LINE access sequence).  This sequence is an sequence of {line-exit,
line-entry} values where the line-exit value equals the line-entry
value and represents one element of the DIAS sequence.  Such a
sequence is hidden from the L2 when successive entries do not both
miss in the I-CACHE.  The DIAS can be derived from the information
available within the L2 if the L2 maintains a Multiprocessor Branch
History Table (MBHT) which it coordinates with the processor BHT via
the BWG information.  The MBHT ENTRY is an extension of the
information  typically found in a BHT.  The information maintained
about branches that were uncovered via the BWG's within individual
processors must be kept on a per-processor basis.  Considering
potential for variability of TYPE B branch information within
different processors as these processors are not all in agreement
about the last action/target of the same branch.  An indicator that
distinguishes between the action/target/...