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Address Generate Interlock History Table

IP.com Disclosure Number: IPCOM000106800D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

The repetition of processor action both delays and productive cycles on code that is repeated should be no surprise. If we assume that instructions are not modified by the program in execution then an address that specifies an instruction will continue to specify the same instruction. If that instruction is a taken branch then the delay in decoding the target of that branch can be reduced by the use of a Branch a History Table (BHT). A BHT does two things:

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This is the abbreviated version, containing approximately 52% of the total text.

Address Generate Interlock History Table

      The repetition of processor action both delays and productive
cycles on code that is repeated should be no surprise.  If we assume
that instructions are not modified by the program in execution then
an address that specifies an instruction will continue to specify the
same instruction.  If that instruction is a taken branch then the
delay in decoding the target of that branch can be reduced by the use
of a Branch a History Table (BHT).  A  BHT does two things:

o   It used the address of the instruction as a surrogate for a
    branch, and

o   It used the address of the instruction as a surrogate for the
    address of the target of the branch.

The first action of the BHT is supported by the idea that the branch
will not be altered by the program between successive executions and
the second relies on the constancy of the target of the branch.
Branch targets are constant despite the fact that they depend on the
values of registers referenced in the branch instructions since the
structure of the code is designed into the program.  Instructions
lines have a strong successor predecessor relationship.  The action
of the program in its execution seems to maintain the constancy of
the target as well as the action of many branch instructions.

      ADDRESS GENERATE INTERLOCK (AGI) - The occurrence of AGI is as
repeatable as the occurrence of branches.  If during the previous
execution of a program segment an AGI occurred then successive
executions of the program segment will also incur an AGI delay.  The
nature of AGI depends on the proximity of the set/use of a register
and this is determined totally from the the instruction images as
they occur in the code.  Typically the first instruction of a pair
will set a register value that the second instruction of a pair will
use for generating an address.  The recording of AGI in anticipation
of their recurrence will certainly be correct but there is no
guarantee that the address of the quantity loaded into the register,
or the value of the quantity loaded into the register will be the
same.  As the same instructions are used to handle different data one
can imagine that the instructions that have an AGI will not always
require the same value from memory in successive executions.  Thus in
creating a...