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Save/Restore of Architected System Registers After Interrupts

IP.com Disclosure Number: IPCOM000106803D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+4]

Abstract

After executing a branch instruction, the contents of the Link register (LK) or Count register (CTR) may be changed. If a previous instruction caused a program interrupt, or if an external interrupt occurred, we need to restore the original contents in the LK and CTR registers. Otherwise, the machine may operate incorrectly due to the changed contents in LK or CTR. For example:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Save/Restore of Architected System Registers After Interrupts

      After executing a branch instruction, the contents of the Link
register (LK) or Count register (CTR) may be changed.  If a previous
instruction caused a program interrupt, or if an external interrupt
occurred, we need to restore the original contents in the LK and CTR
registers.  Otherwise, the machine may operate incorrectly due to the
changed contents in LK or CTR.  For example:

     Load              (causes a program interrupt -- protection
                        violation, e.g.,)
     Branch and Link   (sets the link register to <PC> + 1)

     The program interrupt may not be detected until after the branch
     instruction has executed.  Some method must be used to recover
     the correct contents of the link register.

      Before the invention can be described in detail, a brief
discussion must be given about the superscalar algorithm used (for a
complete description, please refer to Faraydon O. Karim's Superscalar

Algorithm).  Refer to the diagram in Fig. 1.  The fetch/branch unit
fetches 4 instructions per cycle and sends these instructions to the
superscalar control unit.  The superscalar control unit places the
target register addresses for these 4 instructions in a Collision
Vector Table (CVT) that corresponds to the Save Return Address
buffer.  There are 6 CVT tables each having a depth of 4
instructions; thereby, the superscalar microprocessor can be working
on 24 instructions at any particular instant.

      From these instructions, the superscalar control unit
constructs control words and sends these control words to the
instruction queue.  The instruction queue will then dispatch each
control word to the appropriate execution unit.  When an execution
unit completes an instruction, it sends a "done" signal back to the
superscalar control unit, e...