Browse Prior Art Database

RISC Microcontroller Central Processor Unit Timer Model

IP.com Disclosure Number: IPCOM000106809D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR [+2]

Abstract

The FORCES RISC Microcontroller is a Central Processor Unit (CPU) based on the RISC System/6000* architecture. Its design was derived from the RISC Single Chip. It is a single chip implementation that contains a Branch Processor, a Fixed Point Unit, and a combined Data/Instruction cache.

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RISC Microcontroller Central Processor Unit Timer Model

      The FORCES RISC Microcontroller is a Central Processor Unit
(CPU) based on the RISC System/6000* architecture.  Its design was
derived from the RISC Single Chip.  It is a single chip
implementation that contains a Branch Processor, a Fixed Point Unit,
and a combined Data/Instruction cache.

      Behavior prediction is important in doing performance analysis,
comparative analysis, design improvements, and compiler development.
The problem is intensified when large instruction traces are studied,
because the interaction between stages is almost as active as is the
processing of the instructions.

      The solution contained in this disclosure is a TIMER
representing the FORCES RISC Microcontroller pipeline.

      TIMERs are software representations of a Central Processor Unit
complex.  Sometime called 'Register Level Simulator', they represent
a hardware system by modeling it at a very low level, with a great
deal of detail.  The simulation is carried out at the register level,
effectively modeling all the registers used to hold and transfer
information.  In consequence, its time unit is a 'cycle' and it is
its minimum time differentiation possible:  events that take less
than one cycle are not modeled nor considered.

      Within the rigidity imposed by this low level representation,
the solution taken considers flexibility to modify the pipeline or
some of its characteristics.  This allows 'what if' studies and
evaluations of hardware changes and improvements.

The advantages of this invention follow:

      A TIMER provides the project with a modeling tool to predict
behavior and performance of the design at a very early stage.  This
tool guides the design to maximize the performance of the system.
Also it helps to improve the compiler internal CPU pipeline behavior
and idiosyncrasy can be learned through the TIMER to optimize the
scheduling of the instructions created by the compiler.

      Furthermore, design and implementation variation can be applied
easily and exhaustively to study ways to improve performance, or
other aspects of the implementation like protocol implementations
when interacting with external devices.

      The TIMER (or model) implemented represents precisely  the
FORCES RISC Microcontroller Central Processor Unit.  It includes all
the processing (or execution) stages, their interconnection, the
cache, the memory subsystem, and the synchronization between al...