Browse Prior Art Database

Flip Chip Socket Loader/Unloader

IP.com Disclosure Number: IPCOM000106811D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 193K

Publishing Venue

IBM

Related People

Ferguson, D: AUTHOR [+4]

Abstract

Disclosed is a tool for loading and unloading silicon chips to and from a flip chip socket (FCS), without manual handling of the chips, while maintaining chip tracking information. This tool loads silicon chips from Linear Device Banks (LDB's) into FCS modules, which are then transferred to the burn-in process. After burn-in testing, the FCS modules are returned to the tool for unloading. Loading and unloading operations occur in a clean (class 100) environment, requiring about forty seconds per chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Flip Chip Socket Loader/Unloader

      Disclosed is a tool for loading and unloading silicon chips to
and from a flip chip socket (FCS), without manual handling of the
chips, while maintaining chip tracking information.  This tool loads
silicon chips from Linear Device Banks (LDB's) into FCS modules,
which are then transferred to the burn-in process.  After burn-in
testing, the FCS modules are returned to the tool for unloading.
Loading and unloading operations occur in a clean (class 100)
environment, requiring about forty seconds per chip.

      Figs. 1 and 2 show the FCS module 10 used in the burn-in
testers, with Fig. 1 being a plan view while Fig. 2 is a front
elevational view.  The FCS module 10 includes a housing 12, a
substrate 14, a heater 16 and a heatsink 18.  A chamfered corner 19
of housing 12 is used for orientation of module 10.  Substrate 14
includes test probes and a die (not shown) extending upward within a
space surrounded by heater 16.  A chip to be processed (not shown)
may be placed within the die after the removal of heatsink 18 and
heater 16.  Heater 16 includes a thermal sensor (not shown).
External electrical connections to heater 16 and to the thermal
sensor are made through a cable 20.  Each module 10 is identified on
surface 21 by both machine-readable and human-readable markings.

      Figs. 3 and 4 show the chip carrier 22 used as a linear device
bank (LDB), with Figure 3 being a plan view while Figure 4 is a side
elevational view.  Chip carrier 22 is a molded device, with tapered
pockets for holding chips 24.  Chip carrier 22, which also includes
covers 26, is configured with various pocket sizes and configurations
of rows and columns of pockets, to accommodate different sizes of
chips.  Chip carrier 22 also includes an alignment hole 27 and both
machine- readable and human-readable markings on surface 28.  A chip
carrier (not shown) used in the solder reflow process is similar to
chip carrier 22, except that it is composed of a graphite material.

      Fig. 5 is a plan view of an FCS tray 30, which is used for
staging FCS modules 10 (shown in Fig. 1) within the loader/unloader
tool.  Tray 30 is vacuum molded conductive tray with a number of
pockets 32, each of which can hold a module 10.  A chamfered corner
34 in each pocket 32 engages chamfered corner 19 of a module 10 to
assure proper orientation.  Similarly, a chamfered corner 36 of tray
10 assures proper orientation of tray 10 within the tool.

      Fig. 6 is a plan view of a LDB/reflow tray 40, which is used
for staging both LDB chip carriers 22, and similar carriers from the
reflow process, in the loader/unloader tool.  Tray 40 includes a
plate 42, dowel pins 44, guide assemblies 46, bushings 48, and
handles 49.  Each dowel pin 44 extends upward to engage an alignment
hole 27 (shown in Fig. 3) in a chip carrier 22, and each guide
assembly 46 engages an opposite end of the chip carrier 22,
accurately locating the...