Browse Prior Art Database

High Speed True-Complement Generator Circuit

IP.com Disclosure Number: IPCOM000106812D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 77K

Publishing Venue

IBM

Related People

Cantiant, T: AUTHOR [+4]

Abstract

To access a specific location in a memory array requires a decoding system. The most common work decoder circuits use True (T) and Complement (C) values of every address signal. Generally, provide only one address phase is provided, and thus the other phase has to be generated within memory control circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

High Speed True-Complement Generator Circuit

      To access a specific location in a memory array requires a
decoding system.  The most common work decoder circuits use True (T)
and Complement (C) values of every address signal.  Generally,
provide only one address phase is provided, and thus the other phase
has to be generated within memory control circuits.

      In numerous applications, the True Complement Generator (TCG)
circuit has to drive a heavy load, as much as 256 word decoders or
even more.  As these word decoders are in the critical access path,
they have to be driven by a performing TCG circuit.  The following
describes a TCG circuit able to drive an important load at high speed
with excellent noise immunity.

      The principle of the new TCG circuit may be understood by
reference to Fig. 1.  An address A is provided.  When SAL signal is
high, True and Complement addresses are generated (AT and AC) in a
symmetrical manner.  When SAL goes low AT and AC are latched.  The
choice of adequate buffers ensure large loads driving in a very
simple and symmetrical way.

      A typical CMOS implementation of the TCG circuit is illustrated
in Fig.  2.  Initially AT and AC are restored to VDD by WTCG and
WTCGN signals.  At the beginning of a cycle WTCGN is at GND and WTCG
is at VDD.  When address signal is available SAL pulse enables AC and
AT generation.

      Then SAL goes back to GND and addresses are latched by FET
cross-coupling d...