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Graphics Floating Point Engine Fix and Float Registers Consolidation

IP.com Disclosure Number: IPCOM000106818D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR [+3]

Abstract

Due to the high functionality incorporated into single chips CPUs, the necessity to save circuitry in the implementation of the logic has become very important. Algorithmic implementations have to be simplified and solutions have to be found to reduce the circuitry, not only for data handling, but also for control.

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Graphics Floating Point Engine Fix and Float Registers Consolidation

      Due to the high functionality incorporated into single chips
CPUs, the necessity to  save circuitry in the implementation of the
logic has become very important.  Algorithmic implementations have to
be simplified and solutions have to be found to reduce the circuitry,
not only for data handling, but also for control.

      The proposal disclosed is a different approach in the GFPE
implementation of the register renaming section.  These techniques
describe ways to reduce the circuitry used for control logic as well
as circuitry to hold and to handle data.

      The Advantages - A net reduction in the circuitry of the chip
and a simplification in the definition and design of the superscalar
pipeline.

      The superscalar unit is in charge of the renaming function in
the GFPE implementation.  The renaming differentiates between Fixed
Point Unit registers and Floating Point Unit registers: the
implementation has two register files, each of them having the
architected registers plus the renaming registers, as shown in Fig.
1.

      The superscalar, upon receiving the instruction, creates a
control word holding information on the internal representation of
the instruction received.  One type of information stored in the
control word is the pointers to the physical register involved in the
operation to be performed.  The superscalar changes, or renames, the
target register by exchanging the architected register defined in the
instruction for the physical register taken from the collision vector
table (CVT), and sets the lock flag indicating this register is in
use.  Also, the superscalar searches for the instruction source
registers through the renamed register table (RGPR) to replace their
architected values for physical addresses.  When the instruction is
completed by one of the processing units (Fix, Float, or Load/store
units), the target register is unlocked in the lock table, and the
superscalar makes this target register available through the
available register table (AGPR).  If the instruction is dispatched
speculatively, as resulting from the sequential or target path of a
conditional branch, the renamed register table for sequential or
target paths is used.  All these tables: RGPR, AGPR, and lock tables
are duplicated to handle Fixed Point Unit registers as well as
Floating Point Unit registers.  Also, each CVT entry has allocation
and flags for both Fixed Point Unit registers and Floating point Unit
registers.  Fig. 2 diagram describes the functionality of the
superscalarprocess.

      The  size of the register files is dictated by the number of
architected registers (32) plus the number of rename registers
defined by the number of CVT entries (24).

      The implementation proposed in this disclosure is a
simplification of the register files and the handling of the renaming
process.  This is accomplished by  conso...