Browse Prior Art Database

Instruction Translation for Trace-Driven Simulation Timer

IP.com Disclosure Number: IPCOM000106834D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR [+3]

Abstract

For a trace-driven timer to accurately model processor performance of different instruction architectures, it has to assume that the instructions produced by these architectures are close to the instruction traces input to the timer. For today's various RISC architectures this assumption is generally true, but most architectures have some instructions which are unique and not supported by other architectures. Therefore, a trace translation is necessary if these unique instructions could impact the accuracy of performance modelling.

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Instruction Translation for Trace-Driven Simulation Timer

      For a trace-driven timer to accurately model processor
performance of different instruction architectures, it has to assume
that the instructions produced by these architectures are close to
the instruction traces input to the timer.  For today's various RISC
architectures this assumption is generally true, but most
architectures have some instructions which are unique and not
supported by other architectures.  Therefore, a trace translation is
necessary if these unique instructions could impact the accuracy of
performance modelling.

      In an implementation of IBM Power architecture timer, which is
designed capable of modeling other superscalar RISC processors, the
trace translation feature is developed to convert some instructions
in the input traces into target instructions supported by the modeled
processors.  The instructions selected to be translated are those
been used frequently enough to affect the modeling accuracy.  Load
Multiple and Store Multiple instruction in IBM Power architecture are
currently selected to be expanded into either multiple load/store
single instructions or load/store doubles depending upon the target
architectures.  A static translation table can be used to translate
other instructions.

      The translation feature is also helpful to justify any new
instructions to be added in the architecture.  By replacing the new
instruction with existing instructions in...