Browse Prior Art Database

Timer Utilization for Hardware Simulation Verification

IP.com Disclosure Number: IPCOM000106839D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR [+2]

Abstract

Hardware verification of a design implementation implies the testing of the implementation in all possible areas and levels. The usual verification method (using RTX) verifies only the testcase end results (values held in registers and memory). This method does not check the internal hardware state cycle by cycle. Thus it only checks for a correct end product, not for most efficient operation, or correct utilization of internal resources. The usual method for checking internal state cycle by cycle is to write IVP (Implementation Verification Program) testcases. However, because of the complexity of the Graphics Floating Point Engine, the creation of these testcases is not a simple task.

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Timer Utilization for Hardware Simulation Verification

      Hardware verification of a design implementation implies the
testing of the implementation in all possible areas and levels.  The
usual verification method (using RTX) verifies only the testcase end
results (values held in registers and memory).  This method does not
check the internal hardware state cycle by cycle.  Thus it only
checks for a correct end product, not for most efficient operation,
or correct utilization of internal resources.  The usual method for
checking internal state cycle by cycle is to write IVP
(Implementation Verification Program) testcases.  However, because of
the complexity of the Graphics Floating Point Engine, the creation of
these testcases is not a simple task.  To fully test the
functionality of the implementation, the testcases have to anticipate
the hardware's behavior to detect discrepancies between expected and
obtained results.

      The creation of such testcases is complex because what
thesetestcases are doing is software simulation of the hardware
behavior.

      The disclosed technique provides an interface between the
functional simulator and the GFPE TIMER, providing low level hardware
verification without complex IVPs.

      Incorporating the TIMER in the verification process reduces the
need for IVPs to verify the internal state of the superscalar,
instruction queue, and branch units.  The TIMER emulates the hardware
and maintains its own version of the internal state of these units.

The hardware verification process is carried out by three components
as shown in Fig. 1:

1.  Random Testcase Program Generator (RTPG)
    Generates the testcases to be run by the simulator and calculates
    the expected results.

2.  Random Testcase Executor (RTX)
    Execute the testcases generated by  RTPG by invoking  the
    hardware simulator (CEFS), and  comparing the results obtained
    from the simulator with the RTPG's expected results.

3.  Compiled Enhanced Functional Simulator (CEFS)
    This unit is the hardware simulator.  It is called by RTX to
    execute the testcases genera...