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A Protocol for Processing Concurrent Misses

IP.com Disclosure Number: IPCOM000106840D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

Misses are not uniformly distributed in time; rather, they cluster. If a processor may only have one outstanding miss at any moment, this clustering effect will tend to stop the pipeline. Even when multiple outstanding misses are permitted, the first-data-back from the last miss is constrained to wait for the completion of all previous trailing edges. Disclosed is a mechanism that alleviates this serialization.

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A Protocol for Processing Concurrent Misses

      Misses are not uniformly distributed in time; rather, they
cluster.  If a processor may only have one outstanding miss at any
moment, this clustering effect will tend to stop the pipeline.  Even
when multiple outstanding misses are permitted, the first-data-back
from the last miss is constrained to wait for the completion of all
previous trailing edges.  Disclosed is a mechanism that alleviates
this serialization.

      The mechanism consists of two sets of signals that are sent by
the processor to the Storage Control Element (SCE) in the event of a
miss, and a set of returning signals that sent from the SCE to the
processor with each returning doubleword (or whatever the quanta as
determined by the bus width).

      The first set of signals is a tag that identifies which of n
misses the information on the address bus corresponds to when the
miss is generated.  This tag is some number, i (modulo n), where the
ith miss facility is being used to handle the miss at the processor
interface.  Of course, it is this same signal "i"  that is returned
with the data doublewords by the SCE, and n line buffers must be
added to the SCE to hold data after it is fetched from the memory.

      The second set of signals merely indicates one of several ways
that the generated miss is to be handled.  These ways are:

o   NORMAL - process the new miss after the current miss has
    completed, as done in the existin...