Browse Prior Art Database

Method of Accessing Uniquely Identically Addressed Input/Output Ports

IP.com Disclosure Number: IPCOM000106841D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 166K

Publishing Venue

IBM

Related People

Schorn, E: AUTHOR

Abstract

Described is an architectural implementation for use on Personal Computer (PC) systems to enable multiple functions, identical or different, to share the same Input/Output (I/O) port addresses and be uniquely without contention.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Method of Accessing Uniquely Identically Addressed Input/Output Ports

      Described is an architectural implementation for use on
Personal Computer (PC) systems to enable multiple functions,
identical or different, to share the same Input/Output (I/O) port
addresses and be uniquely without contention.

      As PCs become more complex, there arises a need to assign
unique I/O port addresses for each function.  Compatibility issues,
such as vendor function and adapters and prior assignments, place
restrictions on port assignments.  In addition, functions, such as
cache and I/O controllers, may need to be expanded or enhanced.
Placing identical chips in a system to enhance functionality is
desirable because the same port can be used over again, thereby
reducing development expense.  However, identical chips have
identical I/O port addressing which can cause contention problems
when accessed.  In prior art, limitations were required when
attempting to utilize identical chips, such as the use of program
option select (POS) ports.  In this case, the POS ports allowed the
functions to have assignable I/O ports and partially avoided
contention problems.

      The concept described herein overcomes contention problems by
using the POS ports in conjunction with a unique POS port access
machine and daisy chained select feature.  This enables individual
access to each function without contention.  Also, the concept
minimizes the need to make identical and future software
modifications for function support, while adding only one pin to the
primary chip I/O.

      The implementation involves three parts that work together: a)
the traditional POS ports; b) a new, unique POS port access machine;
and c) a daisy chained select feature.  The traditional POS ports
enable software to remap the function's I/O ports.  For example,
depending on the values in the POS ports, a serial port chip may
respond as COM1 or COM2 or ...  COM8 for different sets of addresses
thereby allowing multiple serial ports in the same system.  However,
the chips implementing the serial ports must not have identical POS
port addresses.  If they did, when trying to set up one chip by way
of the common POS port, the response could cause contention.  In
typical channel architecture, a card select line allows access to
chips having identical POS addresses.  However, this is a limited
system dependent resource.  Writing to several ports having the same
address is not a problem, but reading from these same ports can cause
contention problems.

      The POS Port Access Machine (PPAM) appears as a write only
common I/O port address among the functions to be individually
accessed and is relocated identically for each function wishing to
share the I/O addresses.  It controls access to the individual POS
port functions.  The inputs are necessary for the system to write
data to the I/O port along with a POS access enable input and reset
signal.  The machin...