Browse Prior Art Database

Multi-Layer Membrane Probe Card

IP.com Disclosure Number: IPCOM000106849D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Franch, RL: AUTHOR [+3]

Abstract

Disclosed is a multi-level thin film membrane probe card for integrated circuit chip testing. Current membrane probe cards [1,2] have just one patterned metal layer on a thin film material like kapton. This single patterned copper layer contains striplines that end in a bump that contacts the chip pads. These striplines (typically 50 ohm characteristic impedance) are used to deliver both signals and power to the chip. The bottom side is an unpatterned ground plane, for obtaining the characteristic impedance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Layer Membrane Probe Card

      Disclosed is a multi-level thin film membrane probe card for
integrated circuit chip testing.  Current membrane probe cards [1,2]
have just one patterned metal layer on a thin film material like
kapton.  This single patterned copper layer contains striplines that
end in a bump that contacts the chip pads.  These striplines
(typically 50 ohm characteristic impedance) are used to deliver both
signals and power to the chip.  The bottom side is an unpatterned
ground plane, for obtaining the characteristic impedance.

      Among the new features described is the use of vias that can be
arbitrarily placed so that power can be delivered through power
planes in other metal layers in the membrane probe.  This geometry
represents a significant reduction in inductance and resulting L
di/dt noise compared to delivering power through a long stripline.
The self-inductance of a one inch long, 50 um wide stripline is on
the order of 10nH.  Delivering power through a much larger shape of a
power plane results in an order of magnitude less inductance.  Fig. 1
shows one implementation for a 2 patterned-layer membrane probe.
Signals are brought in on the top side from the North and South with
striplines that have co-planar GND strips in between, that are
stitched with vias to a GND plane on the bottom side.  Power is
supplied with a VDD and a VSS plane, which approach from the left and
right.  The VDD plane is located on the top side of the membrane and
the VSS plane is located directly beneath it, on the bottom side.

      Another new feature is the use of de-coupling capacitors on the
membrane itself, rather than on the printed circuit board that the
membrane is joined to.  Again, with the use of vias that can be
arbitrarily placed, clearance islands connected to power planes below
can be fabricated and located within millimeters of the chip.  Chip
capacitors can then be soldered to these islands as shown in Fig. 1.

      The geometry for a multi-level implementation with one ground
plane and 2 parallel power planes is s...