Browse Prior Art Database

Parallel Checksum Calculation Accelerator

IP.com Disclosure Number: IPCOM000106854D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Betcher, CW: AUTHOR [+4]

Abstract

Disclosed is a circuit which may be used to accelerate the calculation of checksum or CRC for a digital data frame.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Parallel Checksum Calculation Accelerator

      Disclosed is a circuit which may be used to accelerate the
calculation of checksum or CRC for a digital data frame.

      By combining bus interface logic with checksum logic (i.e.,
adder or CRC polynomial logic), the checksum for a particular data
frame may be calculated as the data is transferred via DMA from/to
and input/output device.

      Since the calculation is performed simultaneously with data
movement using special purpose hardware (as opposed to a software
algorithm), the CPU is offloaded, improving system throughput.

      For a logic function which performs 8, 16, 32 or "n" bit word
width checksum calculation on byte wide boundaries for a particular
data frame, said frame having a starting address "DFA" and a length
"DFL", assume that the system used for exemplification of the
disclosure has a 32 bit wide data bus.  The function would consist
of:

four - 8 bit checksum/CRC logic circuits (Cc13..0)

four - 8 bit accumulator registers (Acc3..0)

one  - control logic function, consisting of:

     one - 32 bit address register (pointer containing address of
                 next byte in data frame)

     one - 30 bit comparator (compare address bus with data pointer)

     one - 16 bit data frame length down counter

     misc- logic gates and registers

      The control logic block serves to provide CPU access to the
data pointer, data counter and checksum calculat...