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Integrating a Branch History Table into the I-Cache Directory

IP.com Disclosure Number: IPCOM000106859D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

With a single chip design, that chip having both the processor and the cache on the chip, a question as to the placement of a Branch History Table (BHT) within the chip arises. It is the function of a BHT to determine the sequence of I-FETCH operation that are to derive from the I-CACHE and present them in a suitable form to the I-BUFFER and I-REGISTER. Within the I-CACHE there is a directory that locates the target of the I-FETCH within the cache arrays if the instruction requested is within the cache. All these terms having arisen from designs where these quantities where on different chips and a delay existed between the deriving of a result from the cache and supplying it to the I-REGISTER.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Integrating a Branch History Table into the I-Cache Directory

      With a single chip design, that chip having both the processor
and the cache on the chip, a question as to the placement of a Branch
History Table (BHT) within the chip arises.  It is the function of a
BHT to determine the sequence of I-FETCH operation that are to derive
from the I-CACHE and present them in a suitable form to the I-BUFFER
and I-REGISTER.  Within the I-CACHE there is a directory that locates
the target of the I-FETCH within the cache arrays if the instruction
requested is within the cache.  All these terms having arisen from
designs where these quantities where on different chips and a delay
existed between the deriving of a result from the cache and supplying
it to the I-REGISTER.  Clearly a single chip design affords the
opportunity to perform many additional functions within the
cache-access path due to the proximity and availability of current
copies of the GPR's (general purpose registers).  However in this
disclosure we shall consider only those aspects that relate to the
integration of the cache directory and the BHT.

      Organize a BHT on a Cache Line Basis - The directory entry for
each cache line points not only to the array position within the
cache of that line but also to a set of BHT type entries associated
with that line.  A compaction of the entries within the BHT portion
is derived from the aspect that the BHT entry which comprised a
{BRANCH ADDRESS, TARGET ADDRESS} can be shortened as all BRANCH
ADDRESSES (BA) are within the line and it is only necessary to locate
the BA to a HW within line (6-bits/128B line).  If the TARGET ADDRESS
(TA) is within the line as well it can also be specified with 6 bits.
For those branch targets (TA) that exit the line the full address is
required and these can be indicated as positions within a list
associated with the entry.

      The operation of the BHT portion of the cache directory
following a First Access to a New Line (FANL) is to place the BHT
infor...