Browse Prior Art Database

Method for Execution Unit Level Fault Tolerance in Superscalar RISC Processors

IP.com Disclosure Number: IPCOM000106865D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 107K

Publishing Venue

IBM

Related People

Karim, F: AUTHOR [+3]

Abstract

Recent superscalar RISC processors dispatch more than one instruction per clock cycle. They have multiple execution units and support out of order execution. The execution units may include one or more floating point units, fixed point units, and load/store units on a single chip. As such hign circuit densities end in big die sizes, it is probable that the yield will be low. Yield can be increased by salvaging some processor chips that have lesser functional execution units but still support the complete instruction set with some performance degradation. If the fault is associated with one or more execution units, the chips can be salvaged by isolating the faulty execution units. The faulty execution units can be disabled at the chip I/O level during board design achieving static fault tolerance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Execution Unit Level Fault Tolerance in Superscalar RISC Processors

      Recent superscalar RISC processors dispatch more than one
instruction per clock cycle.  They have multiple execution units and
support out of order execution.  The execution units may include one
or more floating point units, fixed point units, and load/store units
on a single chip.  As such hign circuit densities end in big die
sizes, it is probable that the yield will be low.  Yield can be
increased by salvaging some processor chips that have lesser
functional execution units but still support the complete instruction
set with some performance degradation.  If the fault is associated
with one or more execution units, the chips can be salvaged by
isolating the faulty execution units.  The faulty execution units can
be disabled at the chip I/O level during board design achieving
static fault tolerance.  The same isolation techniques also can be
applied during system initialization for dynamic fault isolation, if
self test circuits for the execution units are integrated on the
chip.  These fault isolation techniques at the execution unit level
are not possible unless the execution units are highly independent of
each other with minimal interaction with the control unit that
dispatches the instructions.  The execution unit interface and fault
isolation method described here are for a specific superscalar
processor but are applicable to other superscalar processor
architectures too.

      The superscalar processor has three floating point units and
two fixed point units on a single chip.  There is also one load only
unit and one load/store unit that needs to be synchronized with the
fixed point units.  If only one floating point unit and one fixed
point unit that has synchronization with the load/store unit function
correctly, the processor can support the full instruction set at a
lesser performance.  The execution unit interface on chip with other
units that makes the fault isolation possible is illustrated in the
Figure.

      The execution unit interface (Figure) is identical to the
floating point unit interface in the superscalar RISC processor.
Fixed point unit interface is the same except that the INSTRUCTION
DISCARD signal is not present.  Each execution unit requests an
instruction by asserting the INSTRUCTION REQUEST line when the first
stage of execution unit pipeline is empty.  The superscalar control
provides an instruction on the INSTRUCTION CONTROL WORD lines, if its
instruction buffers are not empty.  The instruction could be executed
immediately, if the operands of the instruction are not LOCKED by the
superscalar control.  The execution unit provides the address for the
operands on the OPERAND REQUEST lines to read...