Browse Prior Art Database

Smart Hibernation

IP.com Disclosure Number: IPCOM000106868D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Inoue, K: AUTHOR [+3]

Abstract

Disclosed is a personal computer system that can preserve the running program execution environment across an indefinite power off period in an efficient manner. This is accomplished by selectively backing up to non-volatile storage those memory blocks modified since the last time when the memory contents were backed up, with the help of a memory controller that is capable of dividing system memory in several blocks and recording qualified write accesses to these blocks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Smart Hibernation

      Disclosed is a personal computer system that can preserve the
running program execution environment across an indefinite power off
period in an efficient manner.  This is accomplished by selectively
backing up to non-volatile storage those memory blocks modified since
the last time when the memory contents were backed up, with the help
of a memory controller that is capable of dividing system memory in
several blocks and recording qualified write accesses to these
blocks.

      The memory controller (1) in the Figure has an address decoder
(2) connected to the higher 12 bits of physical address bus (3) and
memory write signal (4).  The decoder output controls 4096 flip-flop
latches (5) to record write access to the corresponding 4K byte pages
in the 16M byte system memory address space (6) of conventional
personal computer system.  The latches are read by system program (7)
through a 16 bit output port (8) connected to system bus that
presents the contents of 16 latches at a time, cycling through the
4096 latches in 256 read operations.  The memory controller also has
an input port (9) that enables resetting the latches and the latch
read cycle.  The latches are cleared by default at power-on time.

      When the user instructs the system program (7) to prepare the
system for a prolonged power-off period, the system program
initializes the latch read cycle and performs up to 256 reads from
the output port (8) to determine which of...