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Selective Prenormalization of Operands in Floating Point Processors

IP.com Disclosure Number: IPCOM000106870D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Karim, F: AUTHOR [+3]

Abstract

Floating point processors use multiply and add type instructions to perform various arithmetic operations. RISC SYSTEM/6000* family of processors have a fused multiply-add instruction that performs multiply and add operation with one instruction. The instruction format is:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Selective Prenormalization of Operands in Floating Point Processors

      Floating point processors use multiply and add type
instructions to perform various arithmetic operations.  RISC
SYSTEM/6000* family of processors have a fused multiply-add
instruction that performs multiply and add operation with one
instruction.  The instruction format is:

     fma  FRT, FRA, FRC, FRB  /*  FRT <--  (FRA * FRC) + FRB   */

Most of the other floating point arithmetic operations can be derived
from this instruction by manipulating the signs of the operands and
making some of the operands 0 or 1 in hardware.  For instance, a
floating point subtract instruction can be derived by inverting the
sign of FRB and making the FRC operand 1.  The processor
prenormalizes all the operands that are not normalized before
executing the instruction.  Prenormalization operation is a dependent
operation.  If the pipeline of the execution unit has P stages to
execute an instruction with one operand to prenormalize, P+1 cycles
are required (assuming no bypass exists from last stage to the first
stage of the pipe) before another instruction that is not dependent
on the current instruction can be accepted.  If prenormalization
cycle can be avoided, a speed-up of 1/P+1 can be achieved for
instructions that require prenormalization of one operand.  RISC
SYSTEM/6000 can produce floating point numbers that are not
normalized as a result of floating point operation.  However, the
number of such occurrences are not significant compared to the
normalized results produced.  The prenormilization process has
significant impact on the floating point performance if one of the
operands is a result of fixed point unit and gets loaded into the
floating point registers as an operand to the floating point
instruction.  As the operand will be in an intermediate form, it
needs to be prenormalized.  This happens in applications where
integer to float conversion is required and in particular most
graphics and image processing applications for transformations,
filtering, etc.

      Graphics Superscalar RISC Processor has three floating point
units, two fixed point units, and two load/store units to deliver
high performance.  The data flow of the floating point unit is
similar to the RISC SYSTEM/6000 processor floating point unit with
some differences in implementation and function.  RISC SYSTEM/6000 is
capable of performing IEEE double precision floating point
arithmetic.  The multiplication is done by Booth encoded array.  The
pipeline is four stages and also has internal bypasses between the
stages for some dependent instructions.  It could produce results
that are not normalized numbers sometimes.  Graphics Superscalar RISC
Processor, on the other hand, uses CSA tree for multiplication.  Each
floating point unit is capable of performing IEEE single precision
floating point arithmetic.  The pipeline is four stages and has a
bypass from last stage to first s...