Browse Prior Art Database

Area Array Solder Attachment of Thin Film Metalized Ceramic Modules

IP.com Disclosure Number: IPCOM000106872D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Foster, RA: AUTHOR

Abstract

This disclosure suggests a configuration which allows the area array solder attachment of ceramic modules using thin film metalization to organic laminate carriers. C-4 chip attachment without substrate through vias is accomplished by placing the chip on the same side of the substrate as the carrier solder joints.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Area Array Solder Attachment of Thin Film Metalized Ceramic Modules

      This disclosure suggests a configuration which allows the area
array solder attachment of ceramic modules using thin film
metalization to organic laminate carriers.  C-4 chip attachment
without substrate through vias is accomplished by placing the chip on
the same side of the substrate as the carrier solder joints.

      Conventional area array solder attachment of ceramic modules is
performed as illustrated in Fig. 1.  An integrated circuit chip (1)
is C-4 attached atop a ceramic substrate (2) which utilizes
multi-layer thick film technology to provide through via capability
for interconnecting chip C-4's through the substrate to carrier
solder joints.  The substrate (2) is attached and interconnected with
a laminated organic carrier (4) via a plurality of solder joints (3).

      The concept illustrated in Fig. 2 is disclosed.  Through vias
in the substrate are no longer needed as the chip is placed on the
same side of the substrate as the substrate to carrier solder joints
(3).  Chip to carrier interconnections on the substrate may be
fabricated through the use of thin film metallurgy.  The concept is
enabled by the fact that the height required for solder joint
reliability (in (3)) is greater than the accumulated height of the
chip and C-4 solder connections.

      Typical applications utilize a passivation encapsulation
between the chip and the substrate, around the C-4 j...