Browse Prior Art Database

Modelling Technique for Master/Slave LSSD Latches with Gated Clocks

IP.com Disclosure Number: IPCOM000106876D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+3]

Abstract

This invention pertains to modelling "master/slave LSSD latches" in a manner which allows for efficient simulation of large systems using many such latches. The technique allows the pair of latches to be modelled as a single latch element which effectively reduces the amount of work the simulator needs to do in the course of simulating the system behavior during each cycle. Since the development of complex VLSI designs demand large amounts of simulation, the effective savings in terms of real CPU hours used for simulation and the productivity gain due to faster simulation job turn-around time is quite large.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Modelling Technique for Master/Slave LSSD Latches with Gated Clocks

      This invention pertains to modelling "master/slave LSSD
latches" in a manner which allows for efficient simulation of large
systems using many such latches.  The technique allows the pair of
latches to be modelled as a single latch element which effectively
reduces the amount of work the simulator needs to do in the course of
simulating the system behavior during each cycle.  Since the
development of complex VLSI designs demand large amounts of
simulation, the effective savings in terms of real CPU hours used for
simulation and the productivity gain due to faster simulation job
turn-around time is quite large.

      The specific technique described here allows modelling of L1/L2
latch pairs as two "parallel" latch elements as opposed to two
"serial" latch elements.  This offers the advantage of requiring only
one simulation cycle to get through the two latches as opposed to two
for the serial modelling technique.

      This was particularly challenging due to the fact that each of
the latch elements can have independent clock gating terms associated
with them.  These independent gating terms allow for the possibility
that the two latch elements could contain different data during the
same simula- tion cycle (which would prevent the modelling of the
latch pair as a single latch element).  In addition, the L1 latch
could operate in a mode where it acts as a "flush latch", during
which time the input to the latch must be presented at the output of
the latch during the same cycle.  Finally, some of the latches
present both the L1 output and the L2 outputs to the rest of the chip
logic.  These factors lead to tech- ...