Browse Prior Art Database

Integrated Controller with Fine-Tuned Memory Timings

IP.com Disclosure Number: IPCOM000106882D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 84K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+2]

Abstract

Disclosed is an integrated controller having fine-tuned timings providing optimal operation at several clock frequencies, which may include, for example, memory controller, cache controller, bus interface, and Direct Memory Access (DMA) circuits. Such a controller may be used in various products across a range of frequencies. In the fine-tuning process, memory control signals are generated at intervals delayed from the edges of clock signals by delay lines. In this way control timings can be adjusted for optimization despite known differences in system clock frequencies.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Integrated Controller with Fine-Tuned Memory Timings

      Disclosed is an integrated controller having fine-tuned timings
providing optimal operation at several clock frequencies, which may
include, for example, memory controller, cache controller, bus
interface, and Direct Memory Access (DMA) circuits.  Such a
controller may be used in various products across a range of
frequencies.  In the fine-tuning process, memory control signals are
generated at intervals delayed from the edges of clock signals by
delay lines.  In this way control timings can be adjusted for
optimization despite known differences in system clock frequencies.

      If memory control signals are provided based on the edges of
clock signals, without the application of such delay lines, the
limits placed on the resolution of an integrated controller result in
conditions which waste time with various clock frequencies.  For
example, an integrated memory controller may be used in both a 25-MHz
system, having a clock period of 40 ns, and in a 40-MHz system,
having a clock period of 25 ns.  If the memory of such a system
requires a Row Address Select (RAS) precharge time of 55 ns, two
clock pulses (or 80 ns) will be required for RAS precharge in the
25-MHz system, while three clock pulses (or 75 ns) will be required
in the 40-MHz system.  Thus, an additional time of 25 ns is used in
the 25-MHz system, while an additional time of 20 ns is used in the
40-MHz system.  This problem is solved by fine tuning with delay
lines.

      In the case of controlling the memory and bus interface, the
integrated controller provides buffered signals.  As shown in Fig.
1, the memory controller portion 10 of integrated controller 12
provides a Row Address Select (RAS) signal and a Column Address
Select (CAS) signal to a memory redrive...