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Browse Prior Art Database

Frequency Guarding of System Cycle Time Using Integrated Byte Multiply

IP.com Disclosure Number: IPCOM000106886D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 123K

Publishing Venue

IBM

Related People

Adams, S: AUTHOR [+2]

Abstract

Disclosed is a hardware integrated solution to prevent a field programmable clock source from being run at a frequency faster than the designated ship frequency of the machine in which it's installed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Frequency Guarding of System Cycle Time Using Integrated Byte Multiply

      Disclosed is a hardware integrated solution to prevent a field
programmable clock source from being run at a frequency faster than
the designated ship frequency of the machine in which it's installed.

      The implementation of this solution assumes a PLLFS
(Phase-Locked Loop Frequency Synthesizer) which is programmed via an
external control chip that interfaces to the machine control code.
The PLLFS programs the frequency of the system according to the
equation:

(1)                 Fout = Fref x (N/M) where:  Fref is a reference
freq.
                                                N is an 8 bit byte
                                                M is a 6 bit byte

      In the field, N and M are initially set by resistor divider
networks that interface to the control chip.  These bits are loaded
into REG3 of the control chip which then loads them into the PLLFS on
POWER ON.  In the field, another path exists for changing the
frequency via loading REG2 with N and M bits via machine code.  To
provide this flexibility and yet prevent unauthorized access aimed at
increasing the frequency above the ship frequency, circuitry is
embedded in the control chip that prevents this from happening.  Once
data is written to REG2, the function of this circuitry is to perform
a hardware check to verify that the ratio of the new N/M is smaller
or the same as that which is hardwired via the voltage divider
networks.  Specifically, the inequality below is performed:

     (2)                     N(NEW)/M(NEW) <=  N(OLD)/M(OLD)

      The old N and M values are the hardwired bits, which the
control chip stores in REG3.  The new N and M values are the bits
that the machine code has written to REG2 under certain special
conditions.

The circuit performs the above math by first cross multiplying as
follows:

     (3)                     N(new) x M(old) <=  N(old) x M(new)

      Two identical logic functions compute the two sides of this
equation in parallel.  The math is performed as shown below:

                                 N7   N6   N5   N4   N3   N2   N1  N0
                                 x         M5   M4   M3   M2   M1  M0
                              _______________________________________
                               M0N7 M0N6 M0N5 M0N4 M0N3 M0N2 M0N1
M0N0
                          M1N7 M1N6 M1N5 M1N4 M1N3 M1N2 M1N1 M1N0
                     M2N7 M2N6 M2N5 M2N4 M2N3 M2N2 M2N1 M2N0
                M3N7 M3N6 M3N5 M3N4 M3N3 M3N2 M3N1 M3N0
           M4N7 M4N6 M4N5 M4N4 M...