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Deterministic Approach to Measuring Simulation Completeness

IP.com Disclosure Number: IPCOM000106888D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 5 page(s) / 152K

Publishing Venue

IBM

Related People

McNeil, WL: AUTHOR

Abstract

The size, complexity, and long fabrication time of a VLSI chip require that comprehensive simulation be performed. The goal of this simulation is to exercise every function in the chip and to verify that every function works correctly. In the former case, it is necessary to have some measurement of how many functions have been tested. This measurement may be called simulation completeness.

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Deterministic Approach to Measuring Simulation Completeness

       The size, complexity, and long fabrication time of a VLSI
chip require that comprehensive simulation be performed. The goal of
this simulation is to exercise every function in the chip and to
verify that every function works correctly. In the former case, it is
necessary to have some measurement of how many functions have been
tested.  This measurement may be called simulation completeness.

      The simulation completeness process is shown in Fig. 1. As Fig.
1 shows, a simulation testcase is run by the simulator, resulting in
an All Events Trace (AET) dataset being generated.  The AET contains
a record of what value was present on each signal in the design for
each unit of time in the simulation.  The AET is processed by the
completeness function, resulting in a completeness report. This
process is repeated for each testcase; the summary function then
generates a summary report.

      One measure of simulation completeness is a simple check of
each signal in the design to determine what values that signal has
taken on during the course of the simulation.  The four possible
values are zero, one, both zero and one, and neither zero nor one
(uninitializ ed).  This function (hereafter referred to as Structural
Completeness) provides an indication if a signal has been left out of
the simulation.  It does not indicate how completely the signal or
associated functions have been tested.

      A new completeness function (hereafter referred to as Group
Completeness) is defined that will allow exhaustive analysis of all
functions in a design.  The user will define groups of signals and
associated patterns that the Group Completeness function will use as
inputs.  The Group Completeness function will search the AET for the
requested patterns, generate statistics based on the search results,
and create the completeness report.  A new summary function
(hereafter referred to as Group Summary) will summarize the
statistics in a summary report, using the completeness reports as
inputs.

      The Group Completeness and Summary functions will allow
exhaustive analysis o...