Browse Prior Art Database

SPD IOA Bus Hardware Simulator for the 6130/6030 I/O Processor

IP.com Disclosure Number: IPCOM000106904D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 95K

Publishing Venue

IBM

Related People

Chew, PF: AUTHOR

Abstract

Disclosed is a hardware simulator card for the SPD I/O Attachment (IOA) bus designed to test all architected functions on the IOA bus. IOA bus operations are invoked using a "back door" command bus (IEEE- 4888). This differs from the convention of using the I/O processor to set up the IOA to perform the desired IOA bus operations. Other unique features are listed at the end of this article.

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This is the abbreviated version, containing approximately 52% of the total text.

SPD IOA Bus Hardware Simulator for the 6130/6030 I/O Processor

       Disclosed is a hardware simulator card for the SPD I/O
Attachment (IOA) bus designed to test all architected functions on
the IOA bus.  IOA bus operations are invoked using a "back door"
command bus (IEEE- 4888).  This differs from the convention of using
the I/O processor to set up the IOA to perform the desired IOA bus
operations.  Other unique features are listed at the end of this
article.

      A 6 high by 4 wide I/O attachment (IOA) hardware simulator card
for the SPD IOA bus was designed to test all the functions of a
communication I/O processor card (IOP).

      The intelligent IOP contains a 68000 MPU, 512K to 1Meg of
memory and smart interface modules (with DMA).  This IOP plugs into
the SPD I/O system bus of a midrange computer system.  The IOP also
has an I/O attachment (IOA) bus that allows customizing to various
communication functions by attaching adapter cards, such as
SDLC/ASCII/BISYNC protocol adapter, IBM Token ring, etc.

      As a result, the IOA bus (driven by the IOP) contains a rich
number of functions.  Testing all supported function becomes a
problem since each product adapter implements only a subset of the
many features provided by SPD IOA bus architecture.

      The following is some of the major functions:
- IOP bus master DMA into the IOA
- IOA bus master Burst DMA into IOP memory
- IOA bus Cycle Steal DMA into IOP memory
- IOA bus Cycle Steal DMA request pre-empting an IOA master Burst DMA
operation
- IOA Interrupt request 1, pre-empting all DMAs
- Three separate interrupt request
- 255 Manual vectors or autovector for interrupts
- Parity checking
- Physical slot number identification for each IOA on the bus

      The IOA hardware simulator adapter was designed and implemented
to handle all these functions.  The adapter was built usin...