Browse Prior Art Database

Method of Increasing On Chip VDD Decoupling Capacitance Using a Shielded Micro Strip Structure

IP.com Disclosure Number: IPCOM000106908D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+4]

Abstract

Disclosed is a new method of increasing on-chip VDD decoupling capacitance using a shielded micro-strip structure. The VDD bus is sandwiched between the grounded substrate and a grounded conductor, forming a shielded micro-strip structure. As a result, a larger VDD decoupling capacitance is obtained for a given surface area than the previous method where the VDD bus is placed above a grounded conductor which in turn is above the substrate (*).

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Method of Increasing On Chip VDD Decoupling Capacitance Using a Shielded Micro Strip Structure

       Disclosed is a new method of increasing on-chip VDD
decoupling capacitance using a shielded micro-strip structure.  The
VDD bus is sandwiched between the grounded substrate and a grounded
conductor, forming a shielded micro-strip structure. As a result, a
larger VDD decoupling capacitance is obtained for a given surface
area than the previous method where the VDD bus is placed above a
grounded conductor which in turn is above the substrate (*).

      Fig. 1 shows the prior art where the VDD bus is placed above
the ground bus. Compared to the new method where the VDD bus is
placed between the ground bus and the grounded substrate, it not only
has a lower VDD  decoupling capacitance but also requires an
additional area in order to make a contact to the trench capacitor.

      Fig. 2 shows the new method of increasing the VDD decoupling
capacitance.  In the figure, the VDD bus made of the first metal
layer is sandwiched between the substrate and the ground bus made of
the second metal layer, forming a shielded strip line. The trenches
are connected to the VDD bus without requiring an additional contact
area in contrast to the prior art shown in Fig. 1, resulting in area
saving.

      Reference
(*)  N. C. C. Lu, H. Chao, W. Hwang, W. Henkels, T. Rajeevakumar,  H.
Hanafi, L. Terman and R. Franch, "A 20-ns 128-kbitx4 High-Speed DRAM
with 330-Mbit/s Data R...