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Parallel Buffer Management Architecture for High Speed Attachments

IP.com Disclosure Number: IPCOM000106913D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Mei, GG: AUTHOR [+4]

Abstract

Disclosed is an architecture for the buffer management functions in packet switching devices such as network bridges, routers and host- to-network adapters. Packet buffering operations are parallelized using a hybrid bus-switch interconnection network and a multiple- memory-bank buffer organization. The block diagram of the architecture is shown in the figure.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parallel Buffer Management Architecture for High Speed Attachments

       Disclosed is an architecture for the buffer management
functions in packet switching devices such as network bridges,
routers and host- to-network adapters.  Packet buffering operations
are parallelized using a hybrid bus-switch interconnection network
and a multiple- memory-bank buffer organization.  The block diagram
of the architecture is shown in the figure.

      Several types of parallelism have been achieved by the
architecture.
      1. Parallel data movements between multiple network ports
(PMIs) and multiple packet memory banks (PMs):
      Packets enter and leave the device through the PMIs. For
receptions, incoming data are staged in the PMIs and then stored into
the PM buffers.  For transmissions, outgoing data are copied from the
PM buffers, staged in the PMIs, and sent out to the network.  While
packets are stored in the PM, they may be processed by a node
processor (uP) if it is required by the involved protocols.  The
interconnection network of the device directs each PMI/uP data
movement through a separate memory bus (MB) to a PM by the
demultiplexers (DEMUXs) so that data movements for different pairs of
PMI/uP and PM can be done simultaneously.
      2. Concurrent data movement and buffer management command
execution:
      A PMI can issue primitives to the GAM, such as requesting
buffers for reception or transmission, enqueuing received packets for
further disposition, releasing buffers after successful packet
transmissions, and other queuing status checking operations.  A
separate command bus (GAB) is provided in the device for
communicating the command requests and responses between the PMIs and
the...