Browse Prior Art Database

Fast Initialization of Bit Steered Memory

IP.com Disclosure Number: IPCOM000106916D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Prill, R: AUTHOR

Abstract

Disclosed is a method for reducing the initialization or bring-up time of computer memory systems that have bit steering with spare bits. Recording the history of previous spare bit usage on non-volatile media at critical times enables these bits to be steered in immediately on subsequent memory initializations for reduced bring-up time.

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This is the abbreviated version, containing approximately 57% of the total text.

Fast Initialization of Bit Steered Memory

       Disclosed is a method for reducing the initialization or
bring-up time of computer memory systems that have bit steering with
spare bits.  Recording the history of previous spare bit usage on
non-volatile media at critical times enables these bits to be steered
in immediately on subsequent memory initializations for reduced
bring-up time.

      Reliable memory systems often include a spare bit which can be
steered into a bad bit position under program control to correct
memory faults (1).  The initialization process that runs during a
reset or power-on event searches the entire memory for a bad bits.
When a bad bit is found, a spare bit is steered in its place and
memory is reinitialized.  Because this is a time-consuming process,
the bit steering information may be stored in a nonvolatile random
access memory (NVRAM) for use by subsequent power-on or reset events
(2).

      Extending the use of NVRAM for storing the anticipated bit
steering information during other critical events results in faster
initialization at the next power-on or machine reset.  Two critical
events will update the bit steering information: 1) a fatal machine
check due to a memory error, and 2) a power-off condition.

      When a fatal machine check occurs due to a memory error, the
error handler will determine which bit or bits caused the error.  The
error handler will store the anticipated bit steering information on
the NVRA...