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Selective Epitaxial Base With Si/Ge Bandgap for Double Poly Self Aligned Bipolar Transistors

IP.com Disclosure Number: IPCOM000106918D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Burghartz, JN: AUTHOR [+2]

Abstract

Described is a selective epitaxial (epi) base structure for double- poly self-aligned bipolar transistors with Si/Ge bandgap engineering. The selective epi base allows the E-B junction to be butted against an oxide emitter spacer ensure high performance.

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Selective Epitaxial Base With Si/Ge Bandgap for Double Poly Self Aligned Bipolar Transistors

       Described is a selective epitaxial (epi) base structure
for double- poly self-aligned bipolar transistors with Si/Ge bandgap
engineering.  The selective epi base allows the E-B junction to be
butted against an oxide emitter spacer ensure high performance.

      Typically, advanced bipolar transistors may have a basewidth of
60 nm or below.  In addition, Si/Ge bandgap is desirable for the
intrinsic base in order to reduce the resistance without sacrificing
the current gain.  The integration of selective epi base technology
in double-poly self-aligned structures is one way to reduce the
basewidth into the sub-60 nm regime for transistors.  Since the
implementation of Ge has not been demonstrated in mid-temperature epi
(MTE) tools, the concept described herin presents an alternative
method using selective epi growth on top of a Si/Ge low temperature
epi (LTE) film.

      The incorporation of Ge into the base region is realized by
means of an outdiffusion of the base dopant from the selective epi
layer into the LTE.  This occurs during the emitter heat treatment.
Figs.  1a to 3b show the structure with three different emitter
spacer modifications.

      After shallow trench formation occurs, the Si/Ge film is
deposited by means of LTE.  Then oxide and nitride films are
deposited by low pressure chemical vapor deposition (LPCVD) and
etched to a stack.  After depositing the extrinsic base materials,
such as poly/oxide/ nitride, the emitter is opened by means of RIE
using the oxide/nitride stack as a landing pad, as shown in Fig. 1a.
Next, an emitter spacer is formed by means of thermally oxidizing the
poly sidewall of the emitter opening and by oxide deposition and RIE,
as shown in Fig. 1b.

      In case suc...