Browse Prior Art Database

Extended L2 Directory for L1 Residence Recording

IP.com Disclosure Number: IPCOM000106935D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 158K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed is a technique for keeping information on first level cache (L1) line residence in an extended directory at second level cache (L2). It minimizes the impact on L1 hit ratios upon busy L2 replacements.

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Extended L2 Directory for L1 Residence Recording

       Disclosed is a technique for keeping information on first
level cache (L1) line residence in an extended directory at second
level cache (L2).  It minimizes the impact on L1 hit ratios upon busy
L2 replacements.

      Subset rule is often applied in implementing multiple level
cache hierarchies.  Consider a 2-level cache hierarchy in a
multiprocessor system.  Each processor (CPU) has its private
first-level cache (L1).  Each L1 itself can consist of multiple
caches (e.g., I/D-split) and is viewed as the totality.  A
second-level cache (L2) is shared by all CPUs (Figure 1(a)).  For the
purpose of illustration we assume that the line size is the same for
both L1 and L2.   The subset rule requires that each L1 line be
covered by a line in L2.  This generally implies the following
requirements:
      o    The L2 control needs to maintain information regarding
line residence at the L1's.  A typical way for the bookkeeping is to
use a bit-vector RES (with as many bits as the number of CPUs) at
each L2 directory entry to indicate the residence of the L2 line at
the corresponding L1 caches.  L2 control updates the RES tags upon L1
cache miss fetches and upon L1 replacements (due to XI-invalidates or
aging).
      o    Upon replacement of a line from L2 (e.g., due to aging or
I/O channel stores to main storage) those L1 copies (if any, as
indicated by the associated RES tag) will be invalidated.

      A major benefit of the described L1/L2 subsetting is that the
full knowledge of L1 contents at L2 control can reduce unnecessary
signaling to L1s.  For instance, without subset rule, broadcasting
invalidate signals to most/all L1s will be necessary when a line not
resident at L2 is modified (e.g., by channel or by a CPU).  With
L1/L2 subsetting such broadcast signaling can be totally avoided.

      One drawback that we are concerned with in this disclosure is
the impact of subset rule on L1 hit ratios. When the size of L2 is
substantially (e.g., 8 times) larger than the combined size of all
L1s, the impact on L1 hit ratios is not visible with usual workloads.
However, such impact can become very significant when L2 replacements
become frequent, due to the forced L1 line invalidates. Examples of
such a situation are: 1) when L2 is not as big relative to the L1s
(e.g., when large L1s are used); 2) when a CPU is running a numeric
program that demands a large working set; and 3) when the system is
running under multiple logical system partitions.  Such anomaly
occurs due to the fact that, in order to maintain subset information
(e.g., RES tags), physical L2 storage (arrays) is not optimally
utilized for L2 accessing itself.  For instance, consider a certain
line L containing instruction codes (e.g., in the operating system)
that are frequently accessed (read) at all processors.  If relatively
large (e.g., 512K) L1 is used at each CPU, L may most likel...