Browse Prior Art Database

Bus Architecture with Each Slot Capable of Multi-function IDs

IP.com Disclosure Number: IPCOM000106955D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Kimoto, H: AUTHOR [+3]

Abstract

Disclosed are a circuit and a bus architecture which allow an adapter card in a bus slot to have two or more IDs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 84% of the total text.

Bus Architecture with Each Slot Capable of Multi-function IDs

       Disclosed are a circuit and a bus architecture which
allow an adapter card in a bus slot to have two or more IDs.

      The circuit is a bus junction circuit built in a MICRO CHANNEL*
adapter card.  The circuit diagram is illustrated in the figure.

      The circuit consists of a card setup configuration shadow
register, I/O address decode gate, and AND (OR in negative logic)
gates.  When a CPU writes some value to the card setup configuration
register on the planar card, it also writes the value to the shadow
register.  The shadow register holds the value and activates one of
the card setup signals.  The I/O address decode gate passes through
the setup signal only when POS registers (I/O address X'100'-X'107)
are accessed.  This circuit generates multiple -CD SETUP(n) signals
which are not assigned to any slots on the planar card and deliver
each signal to each functional logic part on the adapter card.

      The slot-unique signals except -CD SETUP(n) in the MICRO
CHANNEL Architecture (-CD DS 16(n), -CD SFDBK(n), -CD CHRDY(n), and
-CD DS32(n)) come from each functional logic part on the adapter card
and are ANDed or ORed to provide the MICRO CHANNEL bus signals.

      Note that this circuit does not meet the MICRO CHANNEL
Architecture.  But the circuit is a solution to just combine the
existing two or more MICRO CHANNEL adapter cards.

      Another idea for a bus archi...