Browse Prior Art Database

Transistor Size Optimization for Circuit Cells of VLSI

IP.com Disclosure Number: IPCOM000106965D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 5 page(s) / 182K

Publishing Venue

IBM

Related People

Hsieh, HY: AUTHOR [+2]

Abstract

Disclosed is an approach for obtaining the minimum total transistor size which satisfies a given time delay constraint for a basic VLSI CMOS cell. A set of optimal transistor sizes that provide a delay with circuit analysis accuracy can be obtained using the approximate surface which is generated from a limited number of circuit evaluations for the basic cell.

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This is the abbreviated version, containing approximately 38% of the total text.

Transistor Size Optimization for Circuit Cells of VLSI

       Disclosed is an approach for obtaining the minimum total
transistor size which satisfies a given time delay constraint for a
basic VLSI CMOS cell. A set of optimal transistor sizes that provide
a delay with circuit analysis accuracy can be obtained using the
approximate surface which is generated from a limited number of
circuit evaluations for the basic cell.

      In the past, the transistor sizes of a basic cell were
determined by designers who manually selected and ran various circuit
simulations. This process is time consuming and often sub-optimal.
The disclosed approach is to automate the design process and produce
results with accuracy comparable to circuit simulation in a
computationally efficient manner. The key ingredient of this approach
is the accuracy of the delay calculation which cannot be obtained
with the conventional RC approximation (1-5).

      It is well known that the area(power)-time delay surface of an
IC is a well-behaved smooth surface within a practical region.
Furthermore, the typical characteristics of the area-time delay
surface are well understood. First, the gradient of the surface or
the sensitivity of the time delay due to changes in device area is in
general negative. Second, the curvature of the surface or the second
derivative is in general positive. This disclosed approach takes
advantage of the above characteristics of the surface to achieve
program simplicity and computation efficiency. Our aim is to obtain
an approximate surface to match the optimal area-time delay surface
within a practical region for a basic cell. Moreover the errors
between the approximate surface and the optimal area-time delay
surface should be within circuit analysis accuracy. With this error
property a cell designer can modify a design using the approximate
surface to obtain an optimal design rather than design a new cell and
evaluate its delay. It is possible to obtain a single optimal point
for transistor sizes with circuit analysis accuracy by using a
general-purpose circuit optimizer (6-8).  However, any modification
of the cell requires that the optimization process be repeated.

                            (Image Omitted)

      The disclosed approach uses a limited number of circuit
analysis evaluations to generate an approximate surface for time
delay as a function of device widths in a region around a nominal
point. Fig. 1 shows the initial approximate surface       around the
nominal point in a feasible region. It should be noted that the
domain DO of       should cover the region of interest. A new nominal
point    is obtained by an optimization process. Two steps are
required to obtain this point. First, the optimal on the
approximation surface          is determined. Then the device widths
from this point are used to obtain the corresponding real time delay
using circuit analysis. Fro...