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Optimization Algorithm for Circuit Transistor Sizes

IP.com Disclosure Number: IPCOM000106966D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Hsieh, HY: AUTHOR [+2]

Abstract

Disclosed is an algorithm for obtaining the optimal solution on an approximate surface (see preceding article) to solve the transistor size optimization problem for a basic cell. The optimal solution on the approximate surface will be given in closed form.

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Optimization Algorithm for Circuit Transistor Sizes

       Disclosed is an algorithm for obtaining the optimal
solution on an approximate surface (see preceding article) to solve
the transistor size optimization problem for a basic cell. The
optimal solution on the approximate surface will be given in closed
form.

      First we define the time delay function td as:

                            (Image Omitted)

where wi, i = 1,...,n, is the width of the ith type transistor of a
cell.

      The following time delay function was selected due to its
simplicity and well-defined mathematical properties (see preceding
article).

      The optimization problem to be performed is to minimize the sum
of the widths of all transistors in a cell while meeting the time
delay constraint     , or
where mi is the number of transistors of type i having width wi, and
n is the number of transistor types in a cell.

      There are several standard methods of solving the above
optimization problem (1,2).  The Lagrange multiplier method is chosen
for its simplicity.  To this end we formulate the Lagrange function m
such that
where g is the Lagrange multiplier constant. The necessary condition
for an optimal is
since the time delay function f must satisfy

      As one can see from Eq(5) and Eq(6) that we have n+1 equations
with n+1 unknowns.  Consequently, there should exist a unique
solution.

      Solving Eq(5) and Eq(6) for wi, we can obtain the closed form
solution for the above optimal problem.
where

      All transistor widths wi, i=l,...., n can be computed from
Eq(7) if the Lagrange multiplier g is known.  A set of optimized
solutions with their time delay constraints can be obtained from the
above equations without running further circuit analysis.
Consequently, we can compute a set of optimal points on the
approximate surface for different values of    .

      We optimize our problems on an appro...