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Measurement of Power Bus Noise Sensitivity of VLSI Circuits with Automated Functional Tester

IP.com Disclosure Number: IPCOM000106968D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Franch, RL: AUTHOR [+2]

Abstract

Disclosed is a method for directly measuring if noise on the power supply bus of a VLSI circuit can cause the circuit to malfunction. The basis of the method is to test a chip with a functional tester while electronically injecting a disturbance onto the power supply bus. This disturbance acts in the same fashion as noise on the power supply, but is, however, controlled, and can be injected at a known time, with respect to the chip clock, and has a known amplitude, and a known duration. When the functional tester indicates a failure, then it is known that the disturbance of the power supply voltage with those characteristics is the minimum noise which upsets a circuit.

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Measurement of Power Bus Noise Sensitivity of VLSI Circuits with Automated Functional Tester

       Disclosed is a method for directly measuring if noise on
the power supply bus of a VLSI circuit can cause the circuit to
malfunction.  The basis of the method is to test a chip with a
functional tester while electronically injecting a disturbance onto
the power supply bus.  This disturbance acts in the same fashion as
noise on the power supply, but is, however, controlled, and can be
injected at a known time, with respect to the chip clock, and has a
known amplitude, and a known duration.  When the functional tester
indicates a failure, then it is known that the disturbance of the
power supply voltage with those characteristics is the minimum noise
which upsets a circuit.

      By varying the time, amplitude, and duration of the noise
needed for upset, a detailed "schmoo" of the noise sensitivity is
generated.  The timing of the power supply disturbance is shown in
Fig. 1.  This timing diagram is shown for the case of noise during
the read access of a memory.  The noise is injected with a width wn
and amplitude Vn at a time tn after the chip clock starts the read.
After reading the entire memory and checking for failed data, the
data can be re- written, the noise pulse parameters can be changed,
and the test repeated.

      This method is implemented by adding two components to the
functional tester and modifying the testing program.

      The functi...