Browse Prior Art Database

Zero Dimensional Tunneling Triode

IP.com Disclosure Number: IPCOM000106969D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Chang, THP: AUTHOR [+5]

Abstract

Described is a zero-dimensional GaAs/GaAlAs tunneling triode consisting of a double-barrier quantum dot. The device enables tunneling current between two ohmic contacts to be modulated by means of a Schottky pinched gate. The structure and the process necessary for fabrication are described.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Zero Dimensional Tunneling Triode

       Described is a zero-dimensional GaAs/GaAlAs tunneling
triode consisting of a double-barrier quantum dot.  The device
enables tunneling current between two ohmic contacts to be modulated
by means of a Schottky pinched gate.  The structure and the process
necessary for fabrication are described.

      As a starting point, a double barrier heterostructure of GaAs
and GaAlAs or similar structure is used as the starting material.
Fig. 1 shows the device structure.  Carriers from the top ohmic
source tunnel through the barriers and are collected by a bottom
ohmic drain.  The bias at which resonant tunneling occurs can be
modulated by a Schottky gate.

      The five fabrication steps are as follows:
      1)   A mask defines the size of the dot and is patterned by
means of electron bean lithography, as shown in Fig. 2a.
      2)   Reactive ion etching (RIE), which removes the GaAs
selectively with respect to the GaAlAs, is employed to etch the first
GaAl As barrier, shown in Fig. 2b.
      3)   An annular gate is patterned using electron beam
lithography and lift off, as shown in Fig. 2c. The gate thickness is
less than the height of the dot.
      4)   The surface is then coated with an insulator, such as
silicon nitride.  Vias are defined by means of lithography and RIE,
as shown in Fig. 2d.
      5)   Windows are patterned above the source and the gate.  RIE
is used to create vias t...