Browse Prior Art Database

Method of Generating Net Resistance Constraints From RC Delay

IP.com Disclosure Number: IPCOM000106970D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Jepsen, DW: AUTHOR [+2]

Abstract

Disclosed is a method to generate resistance constraints for the source-sink connections of a net given the RC delay requirements on the source-sink connections. The step is crucial to the control of wire delay due to wire capacitance and resistance during circuit placement and wiring. A model and a method to control the length or resistance of every source to sink pair of each net is described in (1).

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Method of Generating Net Resistance Constraints From RC Delay

       Disclosed is a method to generate resistance constraints
for the source-sink connections of a net given the RC delay
requirements on the source-sink connections.  The step is crucial to
the control of wire delay due to wire capacitance and resistance
during circuit placement and wiring.  A model and a method to control
the length or resistance of every source to sink pair of each net is
described in (1).

      It shall be assumed that a net has a fan-out of F to sinks
S1,...,S1,...,SF, and the sinks are connected to the source in the
form of a "star", i.e., separate segments run to each sink from the
source.  It should be pointed out that this approach can be applied
to other physical wiring configurations connecting the source and
sinks, the star configuration is used here for simplicity.

      Let C be the lumped capacitance of the net, Cg1,...,CgF be the
gate capacitance of the sinks s1,...,sF.  When RC delay becomes
significant, the wire resistance of each course-sink connection
cannot be ignored.  Let R1,...,RF be the resistance from s to s1,...,
sF, and C is proportional to R1 + ... + RF.  It is assumed the
resistance and capacitance are directly proportional to the length of
the wire segments.  Let s and p be, respectively, the average
capacitance per unit length and average resistance per unit length.
Then, the F resistance R1, ..., RF are given by the following F
equations:

                            (Image Omitted)

 find R1, ..., RF s.t.
where kR is the proportional constant s/p (in general kR = kL s/p,
where kL is between 1/F and 1 since some of the source-to-sink paths
share a common wiring path), RCreq(si) is the source-sink delay
requirement on the i-th sink si obtained by slack allocation, and
delay(s, si) gives the RC delay from the output s of the block to the
i-th sink si. The source-sink delay requirement is obtained by
allocating slack to the source-sink connections after performing
timing analysis on a logic network (2).

      The delay, delay(s,si), for the source-sink segment of si, j =
1, F, is
 ti = tCAP + tRES where tCAP is the capacitive component and tRES is
the resistive component of the wire delay, using a form of the Elmore
delay.  When wire resistance is insignificant, tRES << tCAP, it
becomes the capacitive mode.

      For example, in CMOS te...