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Zero Skew Techniques for VLSI Systems Disclosure Number: IPCOM000106971D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 8 page(s) / 296K

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Related People

Huang, K: AUTHOR [+2]


Disclosed are exact zero-skew techniques for optimizing the timing performance of synchronous digital VLSI systems.

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This is the abbreviated version, containing approximately 22% of the total text.

Zero Skew Techniques for VLSI Systems

       Disclosed are exact zero-skew techniques for optimizing
the timing performance of synchronous digital VLSI systems.

      Clock skew is defined as the maximum difference of the delays
from the clock source to the clock pins on latches. Optimization of
the clock skew can dramatically reduce the system's cycle time, and
hence the timing performance.  In contrast, improper clock skew may
sometimes cause clock hazard and system malfunction.  As
interconnection delay is becoming more dominating and design size is
becoming larger, the clock skew is also becoming more significant in
terms of performance optimization.

      Many heuristics have been proposed in the past for clock
routing.  H-tree structures are most widely used, especially in
systolic array designs.  However, all these heuristics focus only on
wire length balancing, rather than the real objective - balancing
clock delay, and are not effective enough for tight skew optimization
as encountered in many of today's high performance designs.

      An exact algorithm that balances the clock delay directly is
disclosed.  It is a general approach that takes into account uneven
loading and buffering effects.  First, a novel linear time
hierarchical delay computation is introduced, then how to model clock
trees for delay analysis is discussed, finally the zero-skew
algorithm is disclosed.

      To develop the zero-skew algorithm, a few terms are first
defined and a novel hierarchical method for computing delays in a
bottom-up fashion is introduced, which is the key to our zero-skew

      Let T represent an RC tree with every node associated with an
index.  It is assumed that the index of the root is O.  A predecessor
of node i is a node resides on the unique path between the root and
node i, but exclusing node i itself.  An immediate predecessor of
node i is a predecessor of node i with no other nodes between them.
Similarly, successors of node i is the set of nodes which have node i
as one of their predecessors.  An immediate successor of node i is a
successor of node i with no other nodes in between.  The root is the
node with no predecessor and the leaf nodes are the nodes with no
successors.  A subtree Ti is defined as the subtree of T formed by
the node i and its successors.  Since T is a tree, there is only one
unique edge between a node and its predecessor.  So branch i is
defined as the edge between node i and its immediate predecessor.

      Let ci be the node capacitance of node i and ri be the
resistance of branch i.  For convenience, if node i is the root, set
ri = O.  Define IS(i) as the set of all immediate successors of node
i.  Then the total subtree capacitance Ci of Ti is defined
recursively as

                            (Image Omitted)

      To calculate the delay, N is defined as the collection of all
nodes on the tree T and N(i,j) be...