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Adder Designs Suitable for Custom Implementation

IP.com Disclosure Number: IPCOM000106980D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Phillips, JE: AUTHOR [+2]

Abstract

Three algorithms exhibiting regularity that are suitable for custom design of a two-to-one adder are presented. These algorithms allow the adder to be implemented using either a two-to-one selector book, a 2x2 AO book, or a combination of 2x2 AOI and 2x2 OAI books. Each of the algorithms is presented followed by a discussion of the critical path of a 32-bit adder implemented using each algorithm.

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Adder Designs Suitable for Custom Implementation

       Three algorithms exhibiting regularity that are suitable
for custom design of a two-to-one adder are presented.  These
algorithms allow the adder to be implemented using either a
two-to-one selector book, a 2x2 AO book, or a combination of 2x2 AOI
and 2x2 OAI books.  Each of the algorithms is presented followed by a
discussion of the critical path of a 32-bit adder implemented using
each algorithm.

      Clearly, a two-to-one carry lookahead adder (CLA) exhibiting
regularity using a maximum width of 2x2-AO gates can be directly
implemented from the CLA equations as:

                            (Image Omitted)

      Implementation of an adder using this direct application of the
carry lookahead equations results in an adder requiring the delay of
one 2W-OR stage, five 2x2-AO stages, and one 2W-XOR stage.

      Using inverting logic, a regular adder design can also be
implemented as an immediate consequence of the previous equations by
producing:
in the first stage:
in the second stage:
in the third stage:
and interleaving the generation of the true and complement values of
group generate and propagates in subsequent stages with proper
choices of superscripts and subscripts.  As a result, the delay
consists of a 2W-NOR delay, three 2x2-OAI delays, two 2x2-AOI delays,
and a 2W-XOR delay.

      Given that fast CMOS gates can also be obtained using a cascode
design in w...