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Compensated Internal Delay Line for VLSI Logic

IP.com Disclosure Number: IPCOM000107134D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 160K

Publishing Venue

IBM

Related People

DeRemer, RL: AUTHOR [+3]

Abstract

Delay measurement and compensation logic increases the accuracy of VLSI chip delay blocks allowing them to replace external delay line components with a resulting enhancement of cost, reliability, and ease of assembly.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Compensated Internal Delay Line for VLSI Logic

       Delay measurement and compensation logic increases the
accuracy of VLSI chip delay blocks allowing them to replace external
delay line components with a resulting enhancement of cost,
reliability, and ease of assembly.

      Delay Blocks on VLSI chips have a substantial delay variation
due to the chip manufacturing process and a lesser (but still
substantial) delay variation due to operating temperature and
voltage. These variations tend to make them unusable for most
applications that require some degree of accuracy.

      This article describes a hardware apparatus and a design
process which improves the accuracy of delay elements made up of
logic delay blocks such that they can be used to replace external
delay lines.

      The essential hardware elements are two:
1.  An apparatus to measure the actual delays of on-chip delay blocks
using the system clock (usually highly accurate) as a reference.
Hereafter this will be referred to as the Calibration Hardware.
2.  A correction apparatus to correct the output such that the
resulting delay values meet the desired accuracy.

      The design process includes logic, layout, and analysis
techniques which together determine the accuracy limits.

      Referring to Fig. 1, the Calibration Hardware works as follows:
1.  Calibration is initiated by resetting a Calibrate Complete latch
in Control Register 9 either by Microprocessor Access 13 or Other
Logic 12.
2.  Calibration State Machine 1 switches Input Selector 3 to a leg
connected to the Calibration State Machine 1.
3.  In step with System Clock 2 the Calibration State Machine 1 sends
a step function signal to Delay String 4 via Input Selector 3.
4.  After a time referenced to System Clock 2 the Calibration State
Machine 1 sends a single clock pulse to Pulse Capture Register 5
causing it to latch certain outputs from Delay String 4.  The outputs
from Delay String 4 attached to Pulse Capture Register 5 indicate how
far the pulse has propagated down Delay String 4.
5.  Calibration Encode Logic 6 generates an encoded number that is
proportional to the distance the pulse has traveled (as described in
the previous step) using the outputs of Pulse Capture Register 5.
6.  After a time which allows for metastability of Pulse Capture
Register 5 the output of the Calibration Encode Logic 6 is gated to
Encode Register 10, the Calibrate Complete latch in the Control
Register 9 is set, and the Input Selector 3 is set to accept the
normal Input 11.  The calibration procedure is then complete.

      Again referring to Fig. 1, the normal usage (following
calibration) is as follows:
1.  The Input 11 is sent to Delay String 4 via Input Selector 3.
2.  One or more Outputs (8a - 8n) are received via Output Selectors
(7a - 7n).  The Output Selectors (7a - 7n) are controlled by Encode
Reg 10 such that they are connected to outputs of Delay String 4
which give the desi...