Browse Prior Art Database

Output Buffer Control Logic

IP.com Disclosure Number: IPCOM000107135D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Iwasa, H: AUTHOR

Abstract

Disclosed is a logic circuit for controlling IC Driver active timing. When a data bus is open, data bits change from high impedance to high or low data. Such signal changing generates current switching noise, crosstalk and other electrical noise. The logic circuit disclosed herein reduces this kind of noise.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Output Buffer Control Logic

       Disclosed is a logic circuit for controlling IC Driver
active timing.  When a data bus is open, data bits change from high
impedance to high or low data. Such signal changing generates current
switching noise, crosstalk and other electrical noise. The logic
circuit disclosed herein reduces this kind of noise.

      This circuit controls the driver active timing by using DTRDY
signal 2 which indicates that the internal data is ready, and
consists of Delay elements 5 and 7 which are connected to enable the
inputs of an output buffer (Fig. 2).

      Fig. 1 shows how the DTRDY signal is generated. This is the
case where a host reads data from an I/O device which has the
disclosed circuit.  The DTRDY signal is generated by the state
machine. This state machine comprises 4 states, from S0 to S3.

      The idle state is S0 (1). If the data sent to the host is
ready, the DREQ signal is active. Then the state moves to S1 at the
next clock and the DTRD signal (which reads data from another device)
is active (2).

      Here, DTRDY is checked by the state machine.  If the previous
data does not remain in the circuit, this signal is inactive and the
state changes to S2. Here, the DTRD signal is still active (3). At
the next clock, data is stored in the circuit by DTRD inactive and
the state moves to S3 (4).

      The state S3 makes the DTRDY signal active (5). The state moves
to S0 and next to S1 by the clock (6). Here,...