Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Improved Thin Film Transistor with Encapsulated Nitride Passivation for High Density/ High Speed SRAM Application

IP.com Disclosure Number: IPCOM000107138D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Chu, JO: AUTHOR [+6]

Abstract

The feasibility of high density SRAM (4M or 16M) has recently been demonstrated (1) using a structure with a stacked polysilicon PMOS thin-film device as a pull-up transistor. This leads to a significant improvement in both packing density and stand-by power. The performance of thin-film devices (or TFT) is inherently inferior to that of devices built on single crystal or epitaxial silicon. The reduction of carrier mobility of TFTs is due to the existence of potential barriers created by the polysilicon grain boundaries.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Improved Thin Film Transistor with Encapsulated Nitride Passivation for High Density/ High Speed SRAM Application

       The feasibility of high density SRAM (4M or 16M) has
recently been demonstrated (1) using a structure with a stacked
polysilicon PMOS thin-film device as a pull-up transistor.  This
leads to a significant improvement in both packing density and
stand-by power.  The performance of thin-film devices (or TFT) is
inherently inferior to that of devices built on single crystal or
epitaxial silicon.  The reduction of carrier mobility of TFTs is due
to the existence of potential barriers created by the polysilicon
grain boundaries.

      A unique fabrication process to optimize the thin-film devices
is proposed here.  Firstly, it was discovered that thin-film
transistors built on top of CVD nitride and with gate nitride
sidewalls result in much better performance (i.e., transconductance,
mobility, sub-threshold slope and on/off current ratio) than those
built on oxide and with oxide sidewalls.  Secondly, annealing in
forming gas at 450~C for 5 hours improves the TFT device performance
significantly over conventional shorter annealing times (e.g., 30
minutes).  It is believed that such a step is important to anneal out
interface states.  Thirdly, thin-film transistors capped with a thin
layer of PECVD nitride (e.g., 1000 Ao) prior to annealing outperform
those without nitride cap.  This can be explained by hydrogen
passivation of grain boundaries and interface states in the
polysilicon.  PECVD nitride films can be a source of the hydrogen,
and it has been reported that...