Browse Prior Art Database

Buffer Management for Primary Rate Communications Adapters

IP.com Disclosure Number: IPCOM000107139D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 195K

Publishing Venue

IBM

Related People

Eijan, UG: AUTHOR [+4]

Abstract

Described is a software and hardware facility for the buffer management of communications devices which use integrated services digital network (ISDN) primary rate adapters. The facility is designed to prevent receive and transmit over-runs and under-runs in a multi-channel environment with a common memory when a trunk (T1) carrier and multiple communications processors share common memory for simultaneous data transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Buffer Management for Primary Rate Communications Adapters

       Described is a software and hardware facility for the
buffer management of communications devices which use integrated
services digital network (ISDN) primary rate adapters.  The facility
is designed to prevent receive and transmit over-runs and under-runs
in a multi-channel environment with a common memory when a trunk (T1)
carrier and multiple communications processors share common memory
for simultaneous data transfers.

      The method enables two processors to access data at the same
rate as is being transferred to or from memory by means of T1 logic.
Also, the method provides the ability to manage the processors, one
of which services transmit and one of which services receive with
processors accessing the same data memory.

      The ISDN primary rate adapter typically has two processors
which serve as digital signal processors (DSPs) to process data to
and from a T1 carrier to data memory devices.  One DSP (DSP1) is used
for transmit, and the other (DSP2) is used for receive.  Generally,
there can be 24 or 31 channels depending on the mode of operation.
The data random-access memory (RAM) is split into 24 or 31 segments
where data is sent or received for each channel.  Microcode running
on both DSPs processes the data.  Foreground microcode directly
accesses the T1 data and processes it for use by the host.  The code
is executed as the result of a periodic interrupt.  Each channel can
be thought of as an individual communications link.

      T1 data is transferred across the T1 line to and from the T1
attachment card by the T1 logic into data RAM by cycle steal of data
into the allocated buffers for each of the 31 channels.  Fig. 1 shows
a data RAM segment of one channel.  The allocation of the receive and
transmit buffers is performed at initialization.  Only DSP2 can
access the receive buffer counter register and transmit buffer
counter register data.  This is done to reduce the number of data
paths in the card, thereby simplifying the design.

      The concept described herein provides a means whereby two
processors which run asynchronously with each other and T1 logic
receive data at the same speed as the T1 line; over-runs or
under-runs are prevented. This is done by checking the advancement of
the hardware counters and by processing the proper number of bytes
for each interrupt. To keep DSP2 up to speed without letting it read
the hardware counter directly, a software counter is used.  An
additional background manager is implemented to periodically check
for a potential over-run or under-run condition.

      The concept is implemented as follows:  In receive foreground
mode, the receive microcode is executed by a DSP2 interrupt routine
synchronized to the T1 line.  The interrupt will come every two
milliseconds which is equivalent to receive buffer counter
advancement of 16 bytes for each channel, as in European mode.
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