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Memory Component Design Methodology for Use With System Error Correction

IP.com Disclosure Number: IPCOM000107145D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 153K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR [+3]

Abstract

A methodology for improving system level error correcting is disclosed. This technique applies changes to the memory components that result in reduced error alignment and improves the probability that complement re-complement error recovery will work successfully. The methodology does not require changes to system level error correction circuitry or algorithms.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Memory Component Design Methodology for Use With System Error Correction

       A methodology for improving system level error correcting
is disclosed.  This technique applies changes to the memory
components that result in reduced error alignment and improves the
probability that complement re-complement error recovery will work
successfully.  The methodology does not require changes to system
level error correction circuitry or algorithms.

      Improvements to system level error correction circuitry (ECC)
in terms of effectiveness can take place several ways. All such
systems benefit from components with improved reliability.  A system
with single error correction can be improved if the probability of
fault alignments can be reduced (or eliminated).  A system with
complement re-complement (or complement re-try) can be improved if
the alignment probability is reduced, or if at least one of the
errors encountered in a double-bit alignment is repeatable. This is
true due to the fact that complement re-try will fail if both bad
bits are not repeatable in nature.  Systems with double error correct
are as well improved by the reduction of alignments of 3 errors or
more.  By applying certain circuit techniques to memory components,
the above-mentioned improvements can be realized.

      To realize an overall improved memory component reliability, an
on-chip ECC Single Error Correct, Double Error Detect (SEC-DED) code
can be implemented.  Although some of the improvements can be
realized without such correction on-chip, additional improvements are
gained by using this on-chip ECC.  One effect of the on-chip ECC
(used across some fraction of the selected bits of a word line from
the memory component) is to improve overall memory reliability.  The
on component ECC when used in such a fashion works to reduce or
eliminate single cell fails (for any reason, including alpha
particle-induced soft errors) and bit line failures.  Since the ECC
uses all of its bits from one word line, word line failures along
with I/O kill, 1/2 chip kills, and whole chip kills would not see any
improvement.

      To further extend the improvement of on-chip ECC for the system
which uses complement re-try, a circuit technique can be applied to
the on-chip ECC system to enhance the probability of the failures to
look repeatable.  This can be accomplished by using the double-error
detect (DED) information to corrupt 2 check bits on chip (see Figs.
1a and 1b).  The corrupted check-bits would be complemented from
their calculated value and stored back bad at RE precharge time.  If
this corruption were not performed, the calculated check bits would
be for the corrupt data and would not be detected on subsequent
reads.  The intent of doing this is to cause a double-bit error to
occur on any subsequent read of the same location.  When a double-bit
error is detected on chip, the information is used to force the I/O
to a predetermined state for rea...