Browse Prior Art Database

GaAs MESFET Differential Current Switch Variable Delay Buffer

IP.com Disclosure Number: IPCOM000107147D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Ewen, JE: AUTHOR

Abstract

Disclosed is a circuit providing a voltage controlled variable delay buffer that can be used in a high-speed voltage-controlled oscillator for integrated clock recovery circuits (1) used in fiber-optic data links.

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GaAs MESFET Differential Current Switch Variable Delay Buffer

       Disclosed is a circuit providing a voltage controlled
variable  delay buffer that can be used in a high-speed
voltage-controlled oscillator for integrated clock recovery circuits
(1) used in fiber-optic data links.

      The basic circuit is shown in Fig. 1 and is based on a GaAs
MESFET differential current switch logic family (2). This circuit
family has the advantage of high-speed, low-pulse distortion, and
minimal delay skew.  All of these characteristics are important for
the VCO in a clock recovery circuit.  The circuit consists of a
differential pair, T1 - T2, driving the load resistors, R1 - R2.
The signal swing is set by the current source, T7 and R3, and the
load resistors.  The reference voltage for this current source, PRF,
can be generated by a number of standard techniques. The outputs of
this current switch, nodes 3 - 4, are buffered by a push-pull stage
consisting of the source follower transistors, T5 - T6, and the
pull-down transistors, T3 - T4.

      A variable current source is connected to node PBIAS. By
varying the current at this node, the delay of the buffer can be
controlled.  By varying only the current in the buffer stage, the
signal swing of the gate does not vary widely which enhances the
noise margins over the tuning range of the gate, and prevents large
signal swings which would overdrive subsequent stages and degrade
performance.

      One possible im...