Browse Prior Art Database

Wafer Level Test and Burn In

IP.com Disclosure Number: IPCOM000107177D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 194K

Publishing Venue

IBM

Related People

Anemojanis, E: AUTHOR [+3]

Abstract

Disclosed is apparatus for testing and burning-in the integrated circuit chips on a wafer. The apparatus allows testing each chip either sequentially or all chips at once, the latter allowing a significant reduction in wafer test time. The apparatus eliminates the need to mechanically probe each chip on the wafer, substituting electronic chip selection. Since wafer level burn-in eliminates the need for module burn-in, the cost of packaging, removing, and replacing failing chips is eliminated. In addition, test and burn-in equipment complexity and staffing costs are significantly reduced. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 31% of the total text.

Wafer Level Test and Burn In

       Disclosed is apparatus for testing and burning-in the
integrated circuit chips on a wafer. The apparatus allows testing
each chip either sequentially or all chips at once, the latter
allowing a significant reduction in wafer test time. The apparatus
eliminates the need to mechanically probe each chip on the wafer,
substituting electronic chip selection. Since wafer level burn-in
eliminates the need for module burn-in, the cost of packaging,
removing, and replacing failing chips is eliminated. In addition,
test and burn-in equipment complexity and staffing costs are
significantly reduced.

                            (Image Omitted)

      At present, wafer level device testing is performed using
mechanical steppers which test each chip sequentially. Burn-in is not
conducted at wafer level; burn-in must wait until the chips have been
tested at wafer level, diced, and mounted onto substrates. Current
burn-in requires those packaged chips to be mounted onto special
cards which allow the application of chip power and stimulus to the
signal inputs during an elevated temperature oven cycle. Failing
chips are removed from substrates, replaced with new chips, and
burned-in again.

      This article provides a design for probing all the chips on a
product wafer through a silicon carrier wafer (the carrier) by means
of electronic circuits and wiring located on the carrier. The carrier
is solder mounted onto the product wafer by means of solder bump
interconnects. The carrier has chip pads in a configuration that is
the mirror image of those on the wafer. The carrier would, therefore,
have to be unique for each chip family having different chip size or
pad configuration. The processes to form the electronic devices,
wiring and terminal pads on the carrier are identical to the
processes for wafer fabrication. The carrier is removed prior to
dicing and may be reused many times.

      In a preferred embodiment, the carrier is larger in diameter
than the product wafer. Carrier terminal pads are located in the ring
left uncovered on the carrier by the wafer. Leads from the terminal
pads of the carrier must be brought out to the tester. In a preferred
embodiment that improves durability of the carrier, a lead frame is
mounted to the carrier. The lead frame is a standard PC board with a
hole slightly smaller than the diameter of the carrier. Polyimide
tape bonds the back of the carrier to the lead frame at the overlap.
Wire bonds establish contact between carrier terminal pads and lead
frame pads.  Edge connector, plug, socket or the like establishes
contact to the tester from the lead frame.

      Since the carrier and wafer are both formed from the same
material, silicon, thermal expansion stresses between the two are
avoided.

      Since every chip site on the carrier must work properly for it
to test every chip site on the product wafer, high carrier yield and
reli...