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Browse Prior Art Database

Line Sharing with Disparate Data in MP Systems

IP.com Disclosure Number: IPCOM000107186D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 7 page(s) / 313K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+5]

Abstract

The use of MP CONSISTENCY WITH CLOCKS as a means of retaining the options for which a FETCH sees or does not see a STORE can be applied to line sharing. The manner in which such a shared line is managed is described. The fetching of a line from a hierarchy which has not been updated by the STORE activity that might have occurred, results in ignoring multiple STORES for a given memory cell and a CLOCK relationship that impacts future choices between FETCHES and STORES. CACHE COHERENCY AND OBSERVABLE ORDER

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This is the abbreviated version, containing approximately 20% of the total text.

Line Sharing with Disparate Data in MP Systems

       The use of MP CONSISTENCY WITH CLOCKS as a means of
retaining the options for which a FETCH sees or does not see a STORE
can be applied to line sharing.  The manner in which such a shared
line is managed is described.  The fetching of a line from a
hierarchy which has not been updated by the STORE activity that might
have occurred, results in ignoring multiple STORES for a given memory
cell and a CLOCK relationship that impacts future choices between
FETCHES and STORES.
CACHE COHERENCY AND OBSERVABLE ORDER

      As shall be shown, the definitions of cache coherency in the
literature are not intended to overlap with the concept of OBSERVABLE
ORDER.  That is to say a multiprocessor cache system may exhibit
cache coherency without conforming to OBSERVABLE ORDER and may
conform to OBSERVABLE ORDER without exhibiting cache coherency.  It
is because of this gap between these two concepts that the
definitions currently in use should be examined in detail.
COHERENCY PRINCIPLE

      Censiur and Feautrier (IEEE Transactions on Computers C-27, 12
(December 1978), 1112-1118) define coherency as follows:  "A memory
scheme is coherent if the value returned by a LOAD instruction is
always the value given by the latest STORE instruction with the same
address."

      Hwang and Briggs (COMPUTER ARCHITECTURE AND PARALLEL PROCESSING
- McGRAW HILL (1984) pages 518-519) define coherency as: "A system of
caches is coherent if and only if a READ performed by any processor i
of a main memory location x (which may be cached by other processors)
always delivers the most recent value with the same address x. "Most
recent" in this context has a special meaning in terms of the partial
ordering of READs and WRITEs of memory throughout the multiprocessor.
However for an intuitive understanding of the problem, it is
sufficient to think of recency in terms of absolute time.  In these
terms, whenever a WRITE is done by one processor i to memory location
x, completion of the WRITE must guarantee that all subsequent READs
by any processor will deliver the new contents of x until another
WRITE to x is completed."

      The second definition clearly subsumes the first and serves to
partially clarify a point not discussed in the first, namely, the
meaning of "latest" or "most recent".  In the process, however, a new
term has been used.  The term refers to the completion of a WRITE.
To say a WRITE is complete when everything is all right is
tautological rather than definitive.
SHOWING THE COHERENCY PRINCIPLE IS WRONG

      The use of MP CONSISTENCY WITH CLOCKS (see the preceding
article) as a means of retaining the options for which a FETCH sees
or does not see a STORE can be applied to line sharing.  The fetching
of a line from a hierarchy which has not been updated by the STORE
activity that might have occurred in another processor, results in
ignoring multiple STORES for a given memory c...